Custom IP Core Generation

Generate HDL IP core from your DUT for deployment to the default system reference design or custom reference design registered with the board

HDL Coder™ can generate a custom HDL IP core that you can deploy to the devices. You can integrate the generated IP core into the default system reference design or into your own custom reference design that you register for the board.

Topics

Generate an IP Core for Intel SoC Platform from MATLAB
Generate a custom IP core to target the Intel^® SoC boards.
Generate an IP Core for Intel SoC Platform from Simulink
Generate a custom IP core to target the Intel SoC boards.
IP Core Generation Workflow for Intel FPGA Boards
Learn how to use the IP Core Generation workflow with standalone FPGA devices and embed the IP core into the reference design.
Custom IP Core Generation
Generate a custom IP core from a model or algorithm using the HDL Workflow Advisor.
Custom IP Core Report
You generate an HTML custom IP core report by default when you generate a custom IP core.

Troubleshooting

Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.