部署
综合脚本并将生成的 HDL 代码部署到 Intel®、Xilinx®、Microchip、Speedgoat® 及自定义 FPGA 板
您可将生成的 HDL 代码部署到通用 FPGA 或 ASIC 平台，或部署到使用软硬件协同设计工作流的平台。使用此工作流的目标设备包括独立 FPGA 板（如 Intel 和 Xilinx FPGA 板）、SoC 平台（如 Intel SoC、Xilinx Zynq® 和 Microchip 平台）及 Speedgoat I/O 模块。要了解有关部署到这些平台的更多信息，请参阅HDL IP 核生成。
函数
hdlsetuptoolpath | Set up system environment to access FPGA synthesis software |
主题
- Generate Synthesis Scripts
You can generate customized synthesis scripts for the following tools:You can also generate a synthesis script for a custom tool by specifying the fields manually.
- Create Custom FPGA Board Definition (HDL Verifier)
Run the New FPGA Board Wizard to setup a custom board.
- FPGA Board Customization (HDL Verifier)
Create a custom FPGA board configuration.
精选示例
Get Started with IP Core Generation from MATLAB Function
Use the MATLAB® HDL Workflow Advisor to generate a customized IP core that blinks LEDs on an FPGA board. This example deploys the generated IP core on the ZedBoard hardware, but you can use any Xilinx® Zynq® platform or Xilinx FPGA with a MicroBlaze processor.
