原生浮点
您可使用 HDL Coder™ 原生浮点支持从浮点设计生成 HDL 代码。处理浮点设计时，HDL Coder 支持：
可部署在 FPGA 或 ASIC 设备上的独立于目标的 HDL 代码生成。
完整的 IEEE-754 特征集，包括非规范数、异常和舍入模式。
数学和三角函数。
与定点设计相比，浮点设计具有更高的精度、更大的动态范围和更短的开发周期。如果设计包含复杂的数学和三角运算，请使用原生浮点技术。
类
hdlcoder.FloatingPointTargetConfig | Floating-point target configuration for floating-point library |
hdlcoder.FloatingPointTargetConfig.IPConfig | IP settings for selected floating-point configuration |
函数
createFloatingPointTargetConfig | Create floating-point target configuration for floating-point library that you specify |
对象
coder.HdlConfig | HDL codegen configuration object |
主题
- Getting Started with HDL Coder Native Floating-Point Support
Learn about the native floating point support in HDL Coder.
- Generate Target-Independent HDL Code with Native Floating-Point
Generate HDL code from floating-point Simulink® models.
- Numeric Considerations for Native Floating-Point
Learn about nearest even-digit rounding, denormal numbers, exception handling, and relative accuracy and ULP considerations.
精选示例
Optimize Feedback Loop Design and Maintain High Data Precision for HDL Code Generation
Optimize a feedback loop design and maintain high data precision for HDL code generation by using native floating point and clock-rate pipelining when generating HDL code from a MATLAB® design.
Generate HDL Code from MATLAB Code by Using Native Floating-Point and Vendor Floating-Point Library IP
Use the floating-point IP provided by the AMD® Vivado synthesis tool to generate HDL code that incorporates HDL Coder™ native floating-point (NFP) and AMD® floating-point IP from MATLAB® code. In this example, you use the MATLAB Workflow Advisor and the command-line interface to generate the HDL Code, test bench, and simulation script files.
