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优化基础知识
R2026a通过应用层次结构展平、延迟平衡或反馈环突出显示等优化，针对目标 FPGA 或 SoC 器件优化设计。应用基础优化有助于生成更加硬件高效的 HDL 代码并对生成的代码进行正确仿真。
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主题
- Introduction to Optimizations in HDL Coder
Learn about speed and area optimizations and how to optimize your design.
- Enabling Optimizations in HDL Coder
Learn the settings that directly impact the speed and area of the generated HDL code.
- Find Feedback Loops
Highlight feedback loops that are inhibiting optimizations.
- Hierarchy Flattening
Flatten subsystem hierarchy to enable more extensive area and speed optimization.
- Optimization with Constrained Overclocking
Optimization with constrained overclocking and how it works.
- Understand Delay Balancing in HDL Coder
Insert matching delays along data paths.
- Use Delay Absorption While Modeling with Latency
Model with latency to absorb design delays and prevent a timing mismatch between the original and generated model.
- Generated Model and Validation Model
The generated model is a model created during HDL code generation that shows the HDL implementation architecture and includes latency.
- Remove Redundant Logic and Unused Blocks in Generated HDL Code
Improve readability of generated HDL code and optimize area usage.
- Optimize Unconnected Ports in HDL Code for Simulink Models
Optimize unused ports in generated HDL code in combination with redundant logic deletion.
- Simplify Constant Operations and Reduce Design Complexity in HDL Coder
Area and timing optimizations that simplify constants and optimize mathematical operations.
- Enable-Based Multicycle Path Constraints
Generate enable-based constraints for synthesis tools to meet timing requirements of multicycle paths in single clock mode.
- Generate Multicycle Path Constraints for Multirate Models
Generate Multicycle Path Constraints for Different Rates and Phases.
- Choose Between Multicycle Path Constraints and Clock-Rate Pipelining
Decide whether to use multicycle path constraints (MCP) or clock-rate pipelining (CRP) to meet timing requirement.
- Iteratively Meet Timing Requirements Using Multicycle Path Constraints for Cadence Genus
Use multicycle path constraints with HDL Workflow Advisor and Cadence® Genus synthesis tools to meet the timing requirements for ASIC devices.
疑难解答
Resolve Delays Not Absorbed During Delay Balancing
Troubleshoot extra latency not absorbed during HDL code generation.
精选示例
Investigate and Resolve Non-Absorbable Latency
Recommendations for troubleshooting common delay balancing issues.
Delay Balancing and Validation Model Workflow in HDL Coder
How HDL Coder™ can automatically balance delays within a model. HDL Coder may introduce additional delays in the HDL implementation for a given model. These delays may be introduced by either certain block implementations or by optimizations for the purpose of improving the efficiency of the hardware implementations. However, introducing delays on only certain paths can result functional behavior that is different from the original intent of the user model, thereby violating functional equivalence between the original user model and the HDL implementation.
Control the Scope of Delay Balancing
Balance delays in specific parts of a design, without balancing delays on the entire design.
Use Multicycle Path Constraints to Meet Timing for Slow Paths
Apply multicycle path constraints in your design to meet timing requirements. Using multicycle path constraints can save area and reduce synthesis run times. For more information, see Enable-Based Multicycle Path Constraints.
Optimize Latency and Area for Multirate Designs
Recommendations for optimal code generation of a multirate design.
