displayCaptureCondition

R2026b

Display overall capture condition

Since R2022a

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Syntax

displayCaptureCondition(DC)

Description

Add-On Required: This feature requires the HDL Coder Support Package for Intel FPGA and SoC Devices add-on.

displayCaptureCondition(DC) displays the signal value comparisons and logical operator that define the overall capture condition. DC is a customized data capture object.

example

Examples

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This example uses a customized data capture object, DC, that defines two signals for both trigger and data capture. Signal A is 1 bit and signal B is 8 bits.

Enable capture condition logic.

DC.EnableCaptureCtrl = true;

To enable capture condition logic, you must select the Include capture condition logic parameter while generating the data capture IP core using the FPGA Data Capture Component Generator tool.

Set up a capture condition to capture data when the FPGA detects a high value on signal A at the same time as signal B is greater than 7.

setCaptureCondition(DC,'A',true,'High');
setCaptureCondition(DC,'B',true,7);
setCaptureConditionComparisonOperator(DC,'B','>');

Combine comparisons of signals A and B into an overall capture condition using an AND operator.

setCaptureConditionCombinationOperator(DC,'AND');

Display the overall capture condition.

displayCaptureCondition(DC);
The capture condition is:
A==High and B>7

Input Arguments

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Customized data capture object, specified as an hdlverifier.FPGADataReader System object.

Version History

Introduced in R2022a

See Also

Objects

Tools