Simple Dual Port RAM
Dual port RAM with single output port
![](simple_dual_port_ram.png)
Libraries:
HDL Coder /
HDL RAMs
Description
The Simple Dual Port RAM block models RAM that supports simultaneous read and write operations, and has a single output port for read data. You can use this block to generate HDL code that maps to RAM in most FPGAs.
The Simple Dual Port RAM is similar to the Dual Port RAM, but the Dual Port RAM has both a write data output port and a read data output port.
Read-During-Write Behavior
During a write operation, if a read operation occurs at the same address, old data appears at the output.
Ports
Input
wr_din — Write data input
Scalar
(default)
Data that you write into the RAM memory location when wr_en
is
true. The data inherits the width and data type from the input signal.
wr_din
can be a double
,
single
, integer
, or a fixed-point
(fi)
object, and can be real or complex.
Data type: scalar fixed point, integer, or complex
Data Types: int8
| int16
| int32
| int64
| fixed point
wr_addr — Write address
Scalar
(default)
Write address.
Address that you write the data into when wr_en
is true. This
value can be either fixed-point(fi)
or integer
,
must be unsigned, and have a fraction length of 0
.
Data Types: uint8
| uint16
| uint32
| uint64
| fixed point
wr_en — Write enable
Scalar
(default)
When wr_en
is true, the RAM writes the data into the memory
location that you specify.
Data Types: Boolean
rd_addr — Read address
Scalar
(default)
Address that you read the data from. This value can be either
fixed-point(fi)
or integer
, must be unsigned,
and have a fraction length of 0
.
Data Types: uint8
| uint16
| uint32
| uint64
| fixed point
Output
rd_dout — Output data from read address
Scalar
(default)
Output data from read address, rd_addr
.
Data Types: single
| double
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| Boolean
| fixed point
| enumerated
| bus
Parameters
Address port width — Address bit width
8 (default)
Minimum bit width is 2, and maximum bit width is 29.
Programmatic Use
Block parameter:
ram_size |
Type: string scalar | character vector |
Value: A minimum value of
2 and maximum value of 29 |
Default:
'8' |
Algorithms
HDL code generated for RAM blocks has:
A latency of one clock cycle for read data output.
No reset signal, because some synthesis tools do not infer a RAM from HDL code if it includes a reset.
Code generation for a RAM block creates a separate file,
blockname.ext
. blockname
is derived
from the name of the RAM block. ext
is the target language file
name extension.
RAM Initialization
Code generated to initialize a RAM is intended for simulation only. Synthesis tools can ignore this code.
Implement RAM With or Without Clock Enable
The HDL block property, RAMArchitecture
, enables or suppresses
generation of clock enable logic for all RAM blocks in a
subsystem. You can set RAMArchitecture
to the following values:
WithClockEnable
(default): Generates RAM using HDL templates that include a clock enable signal, and an empty RAM wrapper.WithoutClockEnable
: Generates RAM without clock enables, and a RAM wrapper that implements the clock enable logic.
Some synthesis tools do not infer RAM with a clock enable. If your synthesis tool does
not support RAM structures with a clock enable, and cannot map your generated HDL code to
FPGA RAM resources, set RAMArchitecture
to
WithoutClockEnable
.
To learn how to generate RAM without clock enables for your design, see the Getting Started with RAM and ROM example. To open the example, at the command prompt, enter:
openExample('hdlcoder/GettingStartedWithRAMAndROMInSimulinkExample');
RAM Inference Limitations
If you use RAM blocks to perform concurrent read and write operations, verify the read-during-write behavior in hardware. The read-during-write behavior of the RAM blocks in Simulink® matches that of the generated behavioral HDL code. However, if a synthesis tool does not follow the same behavior during RAM inference, it causes the read-during-write behavior in hardware to differ from the behavior of the Simulink model or generated HDL code.
Your synthesis tool might not map the generated code to RAM for the following reasons:
Small RAM size: your synthesis tool uses registers to implement a small RAM for better performance.
A clock enable signal is present. You can suppress generation of a clock enable signal in RAM blocks, as described in Implement RAM With or Without Clock Enable.
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has one default HDL architecture.
General | |
---|---|
ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
RAMDirective | Specify whether to map RAM blocks in your design to distributed RAMs, block RAMs, or UltraRAM memory on the target FPGA. See also RAMDirective. |
This block supports code generation for complex signals.
The Simple Dual Port RAM
System block implementation uses a MATLAB System block that uses
the hdl.RAM
System object™. Use this block to perform simultaneous read and write operations. It has a
single output port to read data. In the Block Parameters dialog box of the block, you can
specify an initial value for the RAM.
Use this block to replace the Simple Dual Port RAM block in your model. You obtain faster simulation results when using this block in your model.
Version History
Introduced in R2014a
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