RAM and ROM Blocks

Mimic RAMs and ROMs on hardware using blocks in HDL RAMs library

The HDL Coder block library contains many blocks that you can add to your Simulink^® modeling environment and develop your HDL algorithm. You can use blocks from the HDL Coder library to mimic RAM and ROM blocks on the target device.

To filter the Simulink Library Browser to show only HDL-supported blocks, enter hdllib.

Functions

hdllib Display blocks that are compatible with HDL code generation

Checks

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Overview

HDL Coder Checks in Model Advisor / HDL Code Advisor Overview

Subsystem-Level Checks

Check for invalid top level subsystem

Blocks

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HDL RAMs

Dual Port RAM System	Dual Port RAM block based on the hdl.RAM system object with ability to provide initial value
Dual Rate Dual Port RAM	Dual Port RAM that supports two rates
HDL FIFO	Stores sequence of input samples in first in, first out (FIFO) register
Simple Dual Port RAM System	Simple Dual Port RAM block based on the hdl.RAM system object with ability to provide initial value
Single Port RAM System	Single Port RAM block based on hdl.RAM system object with ability to provide initial value
True Dual Port RAM System	True Dual Port RAM block based on the hdl.RAM system object with ability to provide initial value (Since R2023b)
Simple Tri Port RAM System	Simple Tri Port RAM block based on the hdl.RAM system object with ability to provide initial value (Since R2023b)

Topics

Build a ROM Block with Simulink Blocks
HDL Coder™ does not provide a ROM block, but you can easily build one using basic Simulink blocks.
Use Simulink Templates for HDL Code Generation
Use Simulink model templates for HDL code generation to create efficient hardware designs.

Featured Examples

Getting Started with RAM and ROM in Simulink

Utilize RAM resources in your FPGA design using HDL Coder™.

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