Dual Port RAM System

R2026b

Dual-port RAM that supports simultaneous read and write operations

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  • Dual Port RAM System block

Libraries:
HDL Coder / HDL RAMs

Description

The Dual Port RAM System block models a dual-port RAM that supports simultaneous read and write operations through output ports for read and write data. To configure this block, open the block and set the Type of RAM parameter to dual port. By using this block, you can:

Note

During a write, new data appears at the output of the write port wr_dout of the Dual Port RAM System block. If a read operation occurs simultaneously at the same address as a write operation, old data appears at the read output port rd_dout.

Limitations

  • When you build the FPGA bitstream for the RAM, the global reset logic does not reset the RAM contents. To reset the RAM, implement the reset logic.

  • The RAM address can be either fixed-point (fi) or integer, must be unsigned, and must be between 2 and 31 bits long.

  • You can generate HDL code for Dual Port RAM System blocks that are in resettable subsystems.

  • If the RAMArchitecture model configuration parameter is set to WithoutClockEnable, you cannot generate HDL code for Dual Port RAM System blocks in enabled or triggered subsystems.

Ports

Input

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Data to write, specified as a scalar or a vector. You can write the data into the RAM memory location when the write enable signal at port we is true. This value can be an integer, or of type double, single or half. The value can also be a fi object and can be real or complex.

Bus Support:

You can use non-virtual bus and arrays of buses for HDL code generation.

Data Types: single | double | half | int8 | int16 | uint8 | uint16 | Boolean | fixed point

Address to write, specified as a scalar or a vector. Use this address to write to RAM when the signal at port we is true. This value can be either a fixed-point (fi) or an unsigned integer and must be between 2 and 31 bits long.

Data Types: uint8 | uint16 | fixed point

Write enable, specified as a scalar or a vector. When the signal at the we port is true, the block writes the data into the specified memory location. When the signal at the we port is false, the block reads the value from the memory location specified by rd_addr port.

Note

To use column-write method, the data type must be an integer or a fixed-point.

Data Types: uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

Address to read, specified as a scalar or a vector. Use this address to read the data from the RAM. This value can be either a fixed-point (fi) or an unsigned integer, and must be between 2 and 31 bits long.

Data Types: uint8 | uint16 | fixed point

Output

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Read output data, returned as a scalar or vector. The block reads the old data from the memory location specified by the rd_addr port.

Write output data, returned as a scalar or vector. The block reads the new or old data from the memory location specified by the wr_addr port.

Parameters

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Main

Specify the RAM configuration. HDL Coder™ configures the input and output ports based on the RAM type you select.

  • Single port — Create a single-port RAM with write data, address, and write enable data as inputs and read data as the output.

  • Simple dual port — Create a simple dual-port RAM with write data, write address, write enable, and read address as inputs, and data from the read address as the output.

  • Dual port — Create a dual-port RAM with write data, write address, write enable, and read address as inputs, and data from the read address and write address as the outputs.

  • True dual port — Create a true dual-port RAM with write data a and b, write and read addresses for a and b, and write enable a and b as inputs and data from write addresses a and b as the outputs.

  • Simple tri port — Create a simple tri-port RAM with write data, write address, write enable, and read addresses a and b as inputs and data from read addresses a and b as the outputs.

The code generator dynamically configures the input and output ports of the block based on the RAM type that you specify.

Programmatic Use

Block Parameter: RAMType
Type: character vector, string
Values: Single port | Simple dual port | Dual port | True dual port | Simple tri port
Default: Dual port

Enable this option to allow the hardware to execute a read instruction immediately, without waiting one cycle.

Programmatic Use

Block Parameter: AsyncRead
Type: character vector, string
Values: 'on' | 'off'
Default: 'off'

Select the behavior for write output as New data or Old data:

  • New data — Send out new data at the address to the output.

  • Old data — Send out old data at the address to the output.

Dependencies

To enable this parameter, clear the Use asynchronous read feature in target hardware parameter.

Programmatic Use

Block Parameter: WriteOutputValue
Type: character vector, string
Values: New data | Old data
Default: New data

Specify the initial simulation output of the RAM by using one of these options:

  • A scalar value.

  • A vector with a one-to-one mapping between the initial value and the RAM words.

  • An n-by-m matrix with a one-to-one mapping between the initial values and the RAM words in the RAM banks, where n represents the number of RAM banks and m represents the number of address locations in the RAM block, or vice-versa.

Programmatic Use

Block Parameter: RAMInitialValue
Type: integer, floating point
Values: 0.0 | Scalar | Vector
Default: 0.0

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64

Advanced

Since R2024b

  • When you select this parameter, the RAM delays the input data by one cycle before the output can read it. Use this option to ensure the block is cycle-accurate with the generated HDL code.

  • When you clear this parameter, the RAM reads and outputs the input data immediately, but adds one cycle of latency during HDL code generation. Use this option to leverage clock-rate pipelining when you specify an oversampling value or work with multirate models.

Dependencies

To enable this parameter, clear the Use asynchronous read feature in target hardware parameter.

Programmatic Use

Block Parameter: ModelRAMDelay
Type: character vector, string
Values: 'on' | 'off'
Default: 'on'

Since R2025a

  • When you set this parameter to serial, the code generator infers parallel banks of RAM from vector inputs to RAM System block.

  • When you set this parameter to parallel:

    • The code generator does not scale up RAM consumption with the size of the vector input when you generate HDL Code. Instead, it applies each operation of the input signals one at a time, starting with the first index. Enabling serial access allows you to leverage multicycle RAM access at a faster clock rate while modeling with a vector input at the data rate.

    • If the RAM System block exists in a clock-rate pipelining region, the serialization uses a clock-rate implementation instead of local multirate implementation.

Dependencies

To enable this parameter, clear the Model RAM with one cycle of delay parameter or enable the Use asynchronous read feature in target hardware parameter.

Programmatic Use

Block Parameter: VectorAccess
Type: character vector, string
Values: 'serial' | 'parallel'
Default: 'serial'

Programmatic Use: Add Block

To add the block programmatically, use the add_block function with one of these library block paths as the source.

"hdlsllib/HDL RAMs/Dual Port RAM System"

Example: add_block("hdlsllib/HDL RAMs/Dual Port RAM System","myModel/myBlock",MakeNameUnique="on")

More About

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Extended Capabilities

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C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Version History

Introduced in R2017b

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See Also

Objects

Blocks

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