Simple Dual Port RAM System

Simple Dual Port RAM block based on the hdl.RAM system object with ability to provide initial value

Libraries:
HDL Coder / HDL RAMs

Description

The blocks are MATLAB System blocks that use the hdl.RAM System object™. You can specify the RAM type as Dual port, Simple dual port, Single port, True dual port, or Simple tri port. In terms of simulation behavior, the Dual Port RAM System block behaves similar to the Dual Port RAM, the Single Port RAM System behaves similar to the Single Port RAM, and so on. With the MATLAB System blocks, you can:

Specify an initial value for the RAM. In the Block Parameters dialog box, enter a value for Specify the RAM initial value.
Obtain faster simulation results when you use these blocks in your Simulink^® model.
Create parallel RAM banks when you use vector data by leveraging the hdl.RAM System object functionality.
Obtain higher performance and support for large data memories.

Limitations

When you build the FPGA bitstream for the RAM, the global reset logic does not reset the RAM contents. To reset the RAM, make sure that you implement the reset logic.
The RAM write address can be either fixed-point (fi) or integer, must be unsigned, and must be between 2 and 31 bits long.

Ports

Input

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din — Write data input
`Scalar` (default) | `Vector`

Data that you write into the RAM memory location when we is true. This value can be double, single, half, integer, Boolean or a fixed-point (fi) object, and can be real or complex.

Bus Support:

You can use non-virtual bus and array of buses at the data port for HDL code generation.

wr_addr — Write address
`Scalar` (default) | `Vector`

RAM address that you write the data into. This value can be either fixed-point (fi) or integer, must be unsigned, and must be between 2 and 31 bits long.

Dependencies

To enable this port, set the Specify the type of RAM parameter to Simple dual port or Dual port.

Data Types: uint8 | uint16 | fixed point

we — Write enable
`Scalar` (default) | `Vector`

When we is true, the RAM writes the data into the memory location that you specify. If you set the Specify the type of RAM to Single port, the RAM reads the value in the memory location addr when we is false.

Data Types: Boolean

rd_addr — Read address
`Scalar` (default) | `Vector`

Address that you read the data from the RAM. This value can be either fixed-point (fi) or integer, and must be real and unsigned.

Dependencies

To enable this port, set the Specify the type of RAM parameter to Simple dual port or Dual port.

Data Types: uint8 | uint16 | fixed point

Output

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dout — Read data
`Scalar` (default) | `Vector`

Old output data that the RAM reads from the memory location rd_addr.

Dependencies

To enable this port, set the Specify the type of RAM parameter to Simple dual port.

Parameters

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Specify the type of RAM — RAM type
`Dual port` (default) | `Simple dual port` | `Single port` | `True dual port` | `Simple tri port`

Type of RAM, specified as either:

Single port — Create a single port RAM with Write data, Address, and Write enable as inputs and Read data as the output.
Simple dual port — Create a simple dual port RAM with Write data, Write address, Write enable, and Read address as inputs and data from read address as the output.
Dual port — Create a dual port RAM with Write data, Write address, Write enable, and Read address as inputs and data from read address and write address as the outputs.
True dual port — Create a true dual port RAM with Write data a and b, Write/Read address a and b, and Write enable a and b as inputs and data from write address a and b as the outputs.
Simple tri port — Create a simple tri port RAM with Write data, Write address, Write enable, and Read address a and b as inputs and data from read address a and b as the outputs.

The code generator dynamically configures the input and output ports of the block based on the RAM type that you specify.

Enable asynchronous reads — Use asynchronous read feature in target hardware
`off` (default) | `on`

Use the asynchronous read feature in your target hardware, specified as a check box. Boards that support asynchronous read allow the hardware to execute a read instruction immediately instead of waiting one cycle.

Data Types: Boolean

Specify the output data for a write operation — Write output behavior
`New data` (default) | `Old data`

Behavior for Write output, specified as either:

'New data' — Send out new data at the address to the output.
Old data' — Send out old data at the address to the output.

Specify the RAM initial value — Initial simulation output of RAM
`'0.0'` (default) | `Scalar` | `Vector`

Initial simulation output of the System object, specified as either:

A scalar value.
A vector with one-to-one mapping between the initial value and the RAM words.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

The block has a MATLABSystem architecture which indicates that the block implementation uses the hdl.RAM System object.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline.
RAMDirective	Specify whether to map RAM blocks in your design to RAM blocks on the target FPGA. For UltraRAM mapping, Specify the RAM initial value must be set to `0`. For more details, see RAMDirective.

Complex Data Support

This block supports code generation for complex signals.

Restrictions

The block does not support:

Nested bus at the data port.
Non-zero values at the Specify the RAM initial value when using non-virtual bus input to the data port.

Version History

Introduced in R2017b

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R2024a: Array of Buses Input Support

The block now supports HDL code generation for input data specified as an array of buses.

R2024a: Half-Precision and Boolean Data Support

The block now supports HDL code generation with input data of type Half or Boolean.

Simple Dual Port RAM System

Description

Limitations