流水线

R2026b

通过使用自适应流水线、时钟频率流水线和分布式流水线来优化速度

通过缩短关键路径来改进目标 FPGA 或 SoC 器件设计的时序和时钟速度。您可以通过使用不同流水线方法（例如自适应流水线、时钟频率流水线和分布式流水线）来缩短关键路径。

函数

`hdlcoder.optimizeDesign`	Automatic iterative HDL design optimization
`hdlcoder.supportedDevices`	Show supported target hardware and device details
`coder.hdl.pipeline`	Insert pipeline registers at output of MATLAB expression

hdlcoder.OptimizationConfig hdlcoder.optimizeDesign configuration object

允许设计延迟分布	Allow distributed pipelining and delay absorption optimizations to move design delays
流水线分布优先级	Priority for distributed pipelining and delay absorption optimizations
时钟频率流水线	Insert pipeline registers at faster clock rate than data rate
允许 DUT 输出端口的时钟频率流水线	Pass the outputs from DUT at clock rate
平衡时钟频率流水线 DUT 输出端口	Synchronize DUT outputs while satisfying highest-latency requirements of outputs (自 R2022b 起)
分布式流水线	Enable pipeline register distribution
使用综合估计执行分布式流水线	Use synthesis timing estimates to guide pipeline register insertion (自 R2022a 起)
自适应流水线	Insert adaptive pipeline registers
将查找表映射到 RAM	将查找表映射到块 RAM

	Serializer1D	Convert vector signal to scalar or smaller vectors
	Deserializer1D	Convert scalar stream or smaller vectors to vector signal
	Multiply-Accumulate	Perform a multiply-accumulate operation on the inputs
	Multiply-Add	Multiply-add combined operation

Specify Adaptive Pipelining Settings
Automatic pipeline insertion based on the target device, target frequency, and multiplier word-lengths.
Design Patterns That Benefit from Adaptive Pipelining
For certain design patterns, you must enable the adaptive pipelining optimization to meet the timing requirements.
Optimize Clock Speed for MATLAB Code by Using Adaptive Pipelining
Use the adaptive pipelining optimization in HDL Coder™ to optimize clock speed for a MATLAB^® design.

Specify Distributed Pipelining Settings
Distributed pipelining settings, benefits and costs.
Distributed Pipelining Using Synthesis Timing Estimates
Use synthesis timing estimates for distributed pipelining to more accurately reflect how components function on hardware to better distribute pipelines and increase clock frequency for your target device.
Use Distributed Pipelining Optimization in Models with MATLAB Function Blocks
How to optimize HDL code for MATLAB Function blocks for speed by distributing design delays and generated pipeline stages.

Clock-Rate Pipelining
Pipeline registers insertion at the faster clock-rate instead of the slower data rate.
Increase Clock Frequency Using Clock-Rate Pipelining
This example shows how to apply clock-rate pipelining to optimize slow paths in your design and thereby reduce latency, increase clock frequency and decrease area usage.

Pipelining MATLAB Code
Pipelining helps achieve a higher maximum clock rate by inserting registers at strategic points in the hardware to break the critical path.
Pipeline MATLAB Expressions
Insert registers at output of MATLAB expression.
Constrained Output Pipelining
Constrained output pipelining definition and use case.
Automatic Iterative Optimization
How automatic iterative optimization works, prerequisites and restrictions.