Speed Optimization

Critical path estimation and reduction, pipeline register insertion, loop unrolling, and automated iterative clock frequency optimization

Improve the timing and increase the clock speed of your design for a target FPGA or SoC device by reducing the critical path. You can reduce the critical path by using different pipelining methods. For an overview on speed optimizations, see Speed and Area Optimizations in HDL Coder.

Functions

`hdlcoder.optimizeDesign`	Automatic iterative HDL design optimization
`hdlcoder.supportedDevices`	Show supported target hardware and device details

Classes

hdlcoder.OptimizationConfig hdlcoder.optimizeDesign configuration object

Blocks

expand all

HDL Operations

Deserializer1D	Convert scalar stream or smaller vectors to vector signal
Multiply-Accumulate	Perform a multiply-accumulate operation on the inputs
Multiply-Add	Multiply-add combined operation
Serializer1D	Convert vector signal to scalar or smaller vectors

Topics

Adaptive Pipelining
Automatic pipeline insertion based on the target device, target frequency, and multiplier word-lengths.
Clock-Rate Pipelining
Pipeline registers insertion at the faster clock rate instead of the slower data rate.
Distributed Pipelining
Definition, benefits, and costs of distributed pipelining.
Distributed Pipelining Using Synthesis Timing Estimates
Use synthesis timing estimates for distributed pipelining to more accurately reflect how components function on hardware to better distribute pipelines and increase clock frequency for your target device.
Constrained Output Pipelining
Constrained output pipelining definition and use case.
Automatic Iterative Optimization
How automatic iterative optimization works, prerequisites and restrictions.
Critical Path Estimation Without Running Synthesis
Find the estimated critical paths in your design without using third-party synthesis tools.
Generate Custom Timing Database for Custom Tools and Devices
Create a custom timing generator to characterize custom devices for your custom tools.
Design Patterns That Require Adaptive Pipelining
For certain design patterns, you must enable the adaptive pipelining optimization to meet the timing requirements.
Use Distributed Pipelining Optimization in Models with MATLAB Function Blocks
How to optimize HDL code for MATLAB Function blocks for speed by distributing design delays and generated pipeline stages.
HDL Optimizations Across MATLAB Function Block Boundary Using MATLAB Datapath Architecture
Apply optimizations inside and across MATLAB Function blocks with other Simulink^® blocks.

Related Information

Troubleshooting

Resolve Simulation Mismatch When Pipelining with a Feedback Loop Outside the DUT

Learn how to resolve simulation mismatch issues when using pipeline optimizations with feedback loops.

Featured Examples

Distributed Pipelining: Speed Optimization

Optimize a Simulink® design for speed by using the distributed pipelining optimization.

Open Script

Increase Clock Frequency Using Clock-Rate Pipelining

Apply clock-rate pipelining to optimize slow paths in your design and thereby reduce latency, increase clock frequency and decrease area usage. For more information on how to use clock-rate pipelining, see Clock-Rate Pipelining.

Open Script

Iteratively Maximize Clock Frequency by Using Speed Optimizations

Iteratively maximize the clock frequency for your model using various speed and area optimizations.

Open Script