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Create and Use Code Generation Reports

Report Generation

The HDL Coder™ software creates and displays an HTML code generation report when you select one or more options listed in the table. In the Configuration Parameters dialog box, you can specify the UI options in the HDL Code Generation > Report pane.

GUI optionmakehdl PropertyDependency
Generate traceability reportTraceability

Generate HDL code must be enabled.

Generate resource utilization reportResourceReport

Generate HDL code and Generated model must be enabled.

Generate high-level timing critical path reportCriticalPathEstimation

Generate HDL code and Generated model must be enabled.

Generate optimization reportOptimizationReport

Generate HDL code and Generated model must be enabled.

Generate model Web viewHDLGenerateWebview

Generate HDL code must be enabled.

When you generate code, the Code Generation Report appears in a separate window.

Code Generation Report

The Code Generation Report is an HTML file that includes a Summary, a Clock Summary, a Code Interface Report, and one or more of these optional sections:

  • Traceability report

  • Resource utilization report

  • High-level timing critical path report

  • Optimization report

  • Model web view

The Summary lists information about the model, the DUT, the date of code generation, and top-level coder settings. The Summary also lists model properties that have nondefault values.

The Code Interface Report shows the DUT input and output port names, data types, and bit widths. The report displays links corresponding to each input port and output port in your Simulink® model.

Timing and Area Report

When you select Generate resource utilization report, HDL Coder adds a Timing and Area Report section to the Code Generation Report. This section of the report contains these subsections:

  • High-level Resource Report: The Summary section summarizes multipliers, adders and substractors, and registers consumed by the device under test (DUT).

    The Detailed Report section contains more information on the resources that each subsystem uses. Wherever possible, the detailed report links back to corresponding blocks in your model. The Detailed Report section also contains:

    • A Registers section that displays the total 1-bit register that is calculated as the sum of products over the bit widths of the registers and their frequency of occurrence.

    • A Static Shift operators section and a Dynamic Shift operators section. A static shift is a shift value that is a mask constant. The shift logic does not change. A dynamic shift is a shift value specified as input to a block. Dynamic shifts are more resource-expensive than static shifts and should be used sparingly.

  • Target-Specific Report: When you request target-specific code generation on the model, this subsection shows the resource utilization report.

Optimization Report

When you select Generate optimization report, HDL Coder adds an Optimization Report section, that contains these subsections:

  • Clock-Rate Pipelining: If clock-rate pipelining is enabled for your design, this subsection allows you to gain more insight on how the clock-rate pipelining optimization performed in your model. for more information, see Clock-Rate Pipelining Report.

  • Distributed Pipelining: If a subsystem has the DistributedPipelining option enabled, this subsection displays comparative listings of registers before and after you apply the distributed pipelining transform. For more information, see Distributed Pipelining Report.

  • Streaming and Sharing: Summary and detailed information about the subsystems for which you specify sharing or streaming optimizations and the delay balancing summary. For more information, see Resource Sharing Report and Streaming Report.

  • Delay Balancing: Provides detailed information on pipeline latency, phase delays added at the output ports to match delays along the parallel paths, and delay absorption. For more information, see Delay Balancing Report.

  • Adaptive Pipelining: Displays status of the adaptive pipelining optimization, blocks for which pipeline registers are inserted, and the number of pipeline registers. For more information, see Adaptive Pipelining Report.

  • Hierarchy Flattening: Displays hierarchy flattening status, subsystems that have FlattenHierarchy set to on or off, and the inline HDL files. For more information, see Hierarchy Flattening Report.

  • Target Code Generation: Displays target device summary and target mapping status for the subsystem that has floating-point data types.

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