Create and Use Code Generation Reports

HDL Coder™ generates and displays an HTML code generation report when you generate HDL code from a Simulink^® model that has at least one of the report configuration parameters enabled. The report contains information about the generated code such as:

Resource utilization estimates
Timing estimates
The impact of HDL Coder optimizations
Links tracing code to Simulink blocks

Customize the code generation reports by using the model configuration parameters in the HDL Code Generation > Report settings of the Configuration Parameters dialog box.

Generate Reports

These tables list the sections you can add to your code generation reports. HDL Coder generates the Summary, Clock Summary, and Code Interface Report sections by default.

Report Section	Description	Configuration Parameter	Dependencies
Summary	Contains information about the model, design under test (DUT), date of code generation, and non-default HDL Coder settings.	Enable at least one of the parameters in HDL Code Generation > Report section of the Configuration Parameters dialog box.	In the HDL Code Generation > Global Settings settings, enable Generate HDL code.
Clock Summary	Contains information about the: Base rate of the model Base rate of the DUT Sample time of the outputs Latency of the outputs The report also displays information based on the number of clocks in the model, including: The clock enable signals for single-rate models A clock table for multirate models For more information, see Using Multiple Clocks in HDL Coder.
Code Interface report	Lists the names, data types, and bit lengths of the input and output ports to the DUT. The report displays links to each input port and output port in your Simulink model.

Report Section

Description

Configuration Parameter

Dependencies

Summary

Contains information about the model, design under test (DUT), date of code generation, and non-default HDL Coder settings.

Enable at least one of the parameters in HDL Code Generation > Report section of the Configuration Parameters dialog box.

In the HDL Code Generation > Global Settings settings, enable Generate HDL code.

Clock Summary

Contains information about the:

Base rate of the model
Base rate of the DUT
Sample time of the outputs
Latency of the outputs

The report also displays information based on the number of clocks in the model, including:

The clock enable signals for single-rate models
A clock table for multirate models

For more information, see Using Multiple Clocks in HDL Coder.

Code Interface report

Lists the names, data types, and bit lengths of the input and output ports to the DUT. The report displays links to each input port and output port in your Simulink model.

Timing and Area Reports

Report Section	Description	Configuration Parameter	Dependencies
High-level Resource Report	Summarizes the adders, subtractors, multipliers, registers, and other resources the DUT consumes.	Generate resource utilization report	In the HDL Code Generation > Global Settings settings, enable Generate HDL code.
Target-specific Report	Shows the resource utilization report when you generate target-specific code with an FPGA floating-point library mapping.		In the HDL Code Generation > Global Settings settings, enable Generate HDL code. In the HDL Code Generation > Floating Point settings, set Vendor Specific Floating Point Library to a setting other than `None`.
Native Floating-Point Resource Report	Lists the floating-point operators that your Simulink blocks map to.		In the HDL Code Generation > Global Settings settings, enable Generate HDL code. In the HDL Code Generation > Floating Point settings, enable Use Floating Point.
Critical Path Estimation	Estimates the critical path and the propagation delay along the path. This section estimates the maximum frequency the DUT can run at.	Generate high-level timing critical path report	In the HDL Code Generation > Global Settings settings, enable Generate HDL code. In the HDL Code Generation > Global Settings, in the Model Generation tab, enable Generated model.

Optimization Reports

Report Section	Description	Configuration Parameter	Dependencies
Delay Balancing	Provides detailed information on the: Pipeline latency Phase delays added at the output ports to match delays along parallel paths Delay absorption For more information, see Delay Balancing Report.	Generate optimization report	In the HDL Code Generation > Global Settings settings, enable Generate HDL code. In the HDL Code Generation > Global Settings, in the Model Generation tab, enable Generated model.
Hierarchy Flattening	Displays the hierarchy flattening status, subsystems that have FlattenHierarchy set to `on` or `off`, and the inline HDL files. For more information, see Hierarchy Flattening Report.
Code Reuse	Summarizes where HDL Coder reused generated subsystem code.
Target Code Generation	Displays target device summary and target mapping status when the generated code uses floating-point types.
Streaming and Sharing	Summarizes information about the subsystems you specify sharing or streaming for. For more information, see Streaming Report and Resource Sharing Report.
Clock Rate Pipelining	Details how clock-rate pipelining performed in your model. For more information, see Clock-Rate Pipelining Report.
Distributed Pipelining	Displays comparative listings of the registers before and after you apply the distributed pipelining transform. For more information, see Distributed Pipelining Report.
Adaptive Pipelining	Displays the status of the adaptive pipelining optimization, blocks for which pipeline registers are inserted, and the number of pipeline registers. For more information, see Adaptive Pipelining Report.
Frame to Sample	Contains information about the: Frame-to-sample conversion parameters Input ports and output ports that HDL Coder converted to samples Output latency Input and output ports that map large delays to external memory

Traceability Report and Model Web View

Report Section	Description	Configuration Parameter	Dependencies
Traceability Report	Links lines of the generated code to the corresponding blocks in the Simulink model when possible. Enable this report to use the code view in Simulink to trace between the code and model. For more information, see Navigate Between Simulink Model and HDL Code by Using Traceability.	Generate traceability report	In the HDL Code Generation > Global Settings settings, enable Generate HDL code.
Model Web View	Displays the Simulink model in the HTML code generation report. The model web view requires Simulink Report Generator™. For more information, see Generate Web View of Model in Code Generation Report.	Generate model Web view	In the HDL Code Generation > Global Settings settings, enable Generate HDL code.

Alternatively, you can programmatically customize the code generation reports by setting the properties in this table on or off. Use hdlset_param or makehdl to set these properties.

Report Section	`makehdl` Property	Dependencies
High-level Resource Report	`ResourceReport`	Set `GenerateHDLCode` to `on`.
Target-specific Report		Set `GenerateHDLCode` to `on`, and set `FloatingPointTargetConfiguration` to a vendor-specific floating point library.
Native Floating-Point Resource Report		Set `GenerateHDLCode` and `UseFloatingPoint` to `on`.
Critical Path Estimation	`CriticalPathEstimation`	Set `GenerateHDLCode` and `GenerateModel` to `on`.
Delay Balancing	`OptimizationReport`	Set `GenerateHDLCode` and `GenerateModel` to `on`.
Hierarchy Flattening
Code Reuse
Target Code Generation
Streaming and Sharing
Clock Rate Pipelining
Distributed Pipelining
Adaptive Pipelining
Frame to sample
Traceability Report	`Traceability`	Set `GenerateHDLCode` to `on`.
Model Web View	`HDLGenerateWebView`	Set `GenerateHDLCode` to `on`.

Navigate the Code Generation Report

You can navigate to the code generation report from the Simulink model. For example, suppose you generate a report for the model hdlcoderFocCurrentFixptHdl.slx. Open the model by using this command:

openExample('hdlcoder/ClockRatePipeliningExample','supportingFile','hdlcoderFocCurrentFixptHdl.slx')

In this model, the configuration parameters Generate resource utilization reports and Generate optimization reports are enabled. Build HDL code from the subsystem FOC_Current_Control by using this command:

makehdl('hdlcoderFocCurrentFixptHdl/FOC_Current_Control')

The report opens automatically after code generation. You can also open the report by clicking the link to hdlcoderFoxCurrentFixptHdl_codegen_rpt.html in the MATLAB^® Command Window or by opening the HDL Coder app and clicking Open Report.

Code generation report for the model hdlcoderFocCurrentFixptHdl. The contents pane include the high-level resource and optimization reports.

Click the links in the Contents pane to read the different code generation report sections. The generated report contains a High-level Resource Report section that captures the resource utilization of the generated code. It also contains sections for clock-rate pipelining, distributed pipelining, and other optimizations that capture how HDL Coder optimized the generated code.

You can customize the reports to include only the sections you need. For example, enable the CriticalPathEstimation property to generate a report that includes a Critical Path Estimation section.

makehdl('hdlcoderFocCurrentFixptHdl/FOC_Current_Control', 'CriticalPathEstimation', 'on')

Code generation report for the model hdlcoderFocCurrentFixptHdl. The updated report includes a critical path estimation section.

Use Code Generation Reports to Evaluate Code Before Synthesis

When you select the Generate resource utilization report or Generate high-level timing critical path report parameters, HDL Coder adds a Timing and Area Report section to the code generation report. You can use the timing and area report to evaluate whether the generated code can run with the frequency and resources your hardware requires.

Assess the Area of the Generated Code

The Summary section of the high-level resource report estimates the usage of:

Multipliers
Adders and subtractors
1-bit registers
RAMs
Multiplexors
I/O bits
Static shift operators
Dynamic shift operators

Use the resource report to track and reduce the estimated resource usage of the generated HDL code.

The High-Level Resource Report section also contains the following sections:

The Registers section displays the total number of 1-bit registers. The total is the sum of products over the bit widths of the registers and their frequency of occurrence.
Static Shift Operators and Dynamic Shift operators sections. A static shift is a shift value that is a mask constant. The shift logic does not change. A dynamic shift is a shift value specified as an input to a block. Dynamic shifts are more resource expensive than static shifts.

If the resource usage in the reports exceeds what is available on your hardware, consider applying area optimizations such as resource sharing and streaming to the DUT. Resource sharing and streaming optimize the generated code to use shared hardware resources that reduce the area. For more information, see Area Optimizations.

Assess the Timing of the Generated Code

The Critical Path Estimation section includes an estimate of the combinatorial path in the model with the longest timing delay. HDL Coder uses target-specific timing databases to estimate the critical path of the generated code. If HDL Coder does not have a timing database for your target configuration, generate a target-specific timing database using the genhdltdb function. For more information, see Critical Path Estimation Without Running Synthesis.

The propagation delay of the critical path limits the frequency that the generated code can run at on the target. If the estimated delay of the critical path estimation is too long for the DUT to run at your target frequency, consider optimizing the estimated critical path. The critical path estimation links to a criticalPathEstimated script that highlights the critical path in the generated model. Use this script to identify the estimated critical path in your generated model, and then add delays in your original Simulink model to break the critical path.

Additionally, HDL Coder optimizations can optimize the timing of the critical path and increase the maximum frequency of the DUT. For more information, see Speed Optimizations.

Assess the Impact of Optimizations

If the reported timing or area usage do not meet requirements, you can optimize the original model and generate code from it again before synthesis. After generating code, use optimization reports to understand how HDL Coder optimized the DUT or why it did not apply specific optimizations. Use the optimization reports to identify obstacles to optimization and improve the timing and area of the DUT.