Parallel Link Design

Design parallel links such as DDR

The Parallel Link Designer app provides a dedicated system-level design and analysis environment for parallel links. Capture your parallel link designs graphically and experiment with different physical layouts and parameter sweeping to determine setup/hold timing and voltage margins for high-speed parallel links. Analyze parallel interfaces for compliance with timing and signal integrity constraints.

Use the Parallel Link Designer app to configure parallel links. Set simulation parameters, specify corner conditions, and define stimulus patterns. Set up pre-layout analysis to run SPICE and to conduct waveform and timing data analysis to analyze your custom parallel links. View and interpret the results using the Signal Integrity Viewer app. You can also set up and analyze the post-layout PCB database of your parallel link design if you have a license for RF PCB Toolbox™. You can modify the stackup and padstack models and customize vias and see how the changes impact your design.

Featured Examples

DDR5 Implementation Kit

Implement a 1-slot generic DDR5 RDIMM interface for pre-layout analysis or post-layout verification.

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Low-Power DDR5 Architectural Kit

Implement a low-power DDR5 (LPDDR5) interface for pre-layout analysis or post-layout verification.

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GDDR6 x32 Architectural Kit

Implement a 32-bit GDDR6 interface for pre-layout analysis or post-layout verification.

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DDRx Timing and Waveform Mask Analysis

Use the Parallel Link Designer app to perform timing analysis for the DDR (Double Data Rate) family of memory interface protocols. You can use either Setup and Hold margins or by waveform eye-diagram compliance masks to perform the timing analysis. The DDR Memory Down (DDR4_MD) example kit uses both timing and waveform mask analysis. Specifically for DDR4 systems, timing analysis is performed on clock-address/command interface, and waveform compliance masks are applied to strobe-data(DQS-DQ) interface. Other DDR types may use only timing analysis, or only waveform mask analysis or a blend depending on individual standards.

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Post-Layout of DDRx Interface with CPU and DIMMs

Demonstrates the use of Parallel Link Designer in the Signal Integrity Toolbox™ in MATLAB® to set up a post-layout analysis of a DDRx interface on a Main Board having a CPU connected to two DIMM slots to verify that waveform quality and timing margins are met by the PCB database. Many of the steps illustrated in this example are also applicable to Serial Link Designer for post-layout analysis of SERDES links.

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DDR5 IBIS-AMI with Clock Forwarding

Use Signal Integrity Toolbox™ for MATLAB® to analyze a DDR5 interface with the IBIS-AMI feature Clock-Forwarding enabled for analysis of system margins. IBIS BIRD 204, "DQ_DQS GetWave Flow for Clock Forwarding Modeling," adds the ability to pass in an external Clock signal (or Strobe, as appropriate) to an Address (or Data) IBIS-AMI receiver GetWave model using the clock_times pointer defined by the IBIS specification. A new AMI Reserver Parameter, Rx_Use_Clock_Input, is used to enable this functionality.

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