Configure Parallel Link Projects
R2026bUsing the Parallel Link Designer app, you can set up simulation parameters, specify corner conditions, introduce lossy transmission lines, and include jitter and noise in your projects. You can import S-Parameter data and use it in your projects. You can also set up the solution space to include variable groups and permutation mode to reduce the number of simulations required to reach an optimal solution.
Apps
| Parallel Link Designer | Analyze PCB designs for parallel link applications |
| Clock Domain Editor | Edit clock domain entries (Since R2024a) |
Functions
ibischk | Validate IBIS-related files according to IBIS Open Forum (Since R2026b) |
Topics
- Set Up Project Library in Parallel Link Designer
Learn how Parallel Link Designer organizes projects, interfaces, and library elements.
- Simulation Parameters Used in Parallel Link Design
Set parameters to control SPICE simulation and statistical, time domain, and waveform analysis.
- Specify Corner Conditions in Parallel Link Design
Specify process corners and etch corners to simulate in parallel link project.
- S-Parameters in Parallel Link Projects
Learn how to import S-Parameters and use it in analysis.
- STAT Mode
Learn how STAT mode works in the Parallel Link Designer app.
- Solution Space
Solution space variables, permutation mode and case mode.
- Parts
Create and edit parts for pre-layout and post-layout simulation.
- IBIS and Timing File Preprocessor
Programmatically configure timing and IBIS files.
- Model Lossy Transmission Lines in Parallel Link Designer
Learn the mathematics behind the lossy multi-conductor transmission line models.
- Loss in Transmission Line Corners
Learn how loss behaves in various transmission line corners.
- Stimulus Patterns in Parallel Link Design
Define stimulus patterns for time domain analysis in parallel link project.
- Model Jitter and Noise While Designing Parallel Link
Add TX clock jitter, RX clock jitter, RX clock recovery jitter, and noise.
