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sldvtimer

Identify, change, and display timer optimizations

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Syntax

status = sldvtimer
status = sldvtimer(value)
status = sldvtimer(sldvdata)
status = sldvtimer(sldvdata,display)
status = sldvtimer(model)

Description

status = sldvtimer returns a status of 1 if timer optimizations are enabled for Simulink® Design Verifier™ test generation. Otherwise, sldvtimer returns a status of 0.

status = sldvtimer(value) enables or disables timer optimizations for Simulink Design Verifier test generation.

status = sldvtimer(sldvdata) indicates if timer optimizations are recorded in Simulink Design Verifier data file sldvdata. If timer optimizations are recorded, the function returns a status of 1. If timer optimizations are not recorded, the function returns a status of 0. If sldvdata does not have information about the timer optimizations, the function returns a status of -1.

status = sldvtimer(sldvdata,display) indicates if timer optimizations are recorded in Simulink Design Verifier data file sldvdata and identifies model items that are part of recognized timer patterns when display is true. If timer optimizations are recorded, the function returns a status of 1. If timer optimizations are not recorded, the function returns a status of 0. If sldvdata does not have information about timer optimizations, the function returns a status of -1.

status = sldvtimer(model) displays timer patterns in the model that you can optimize for Simulink Design Verifier test generation.

example

Examples

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Open Live Script

Using the sldvtimer function to optimize model timers, increase the number of test generation objectives met during Simulink Design Verifier test generation analysis.

The example model has timers timer_1 and timer_2 in a Stateflow® chart.

1. Open the model:

open_system("ex_sldvtimer_control");

sldvtimer_sf.png

2. On the Design Verifier tab, in the Mode section, select Test Generation, then click Generate Tests.

The Simulink Design Verifier log dialog box displays that:

  1. Test generation exceeded time limit

  2. 28 of 32 objectives satisfied

sldvtimer_information.png

3. The Simulink Design Verifier Errors information dialog box indicates that Test generation did not optimize timer patterns.

4. To enable the timer optimizations, in the MATLAB® Command Window, enter:

sldvtimer(1)

5. On Design Verifier pane in configuration parameter window, set the Maximum analysis time to 50 s.

6. To generate test cases, on the Design Verifier tab, in the Mode section, select Test Generation, then click Generate Tests.

The test generation analysis completes and the software generates the test cases.

Input Arguments

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Logical value to enable timer optimizations.

true to enable timer optimizations.
false (default) to disable timer optimizations.

Name of the data file that contains the timer optimization data.

Logical value to identify model objects that are part of recognized timer patterns.

true to identify model objects that are part of recognized timer patterns.
false (default) not to identify model objects that are part of recognized timer patterns

Handle to a Simulink model

Output Arguments

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Outcome of attempt to record timer optimization, which returns an integer value.

Logical Value ReturnedStatus of Timer Optimizations
1Timer optimizations recorded.
0Timer optimizations not recorded.
-1sldvdata does not have information about timer optimizations.

Limitations

If relational boundary objectives are included for test case generation, sldvtimer can optimize fewer timers. For information on relational boundary objectives, see Relational Boundary.

Version History

Introduced in R2012a

See Also

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