LTE OFDM Demodulator

The block accepts input data either at maximum rate of 30.72 MHz, or at a sample rate corresponding to NDLRB. The input sampling rates for NDLRB values 6, 15, 25, 50, 75, and 100 are 1.92 MHz, 3.84 MHz, 7.68 MHz, 15.36 MHz, 30.72 MHz, and 30.72 MHz, respectively.

When you set the Input data sample rate parameter to Use maximum input data sample rate, the block operates based on the demodulation parameters (NDLRB and CP prefix type) and provides output data along with an output valid signal to the next block.

When you set the Input data sample rate parameter to Match input data sample rate to NDLRB, the block generates an output ready signal and controls the input at a rate with respect to the NDLRB. The block accepts data samples with respect to the NDLRB when the ready signal is 1 (true).

This figure shows a Logic Analyzer waveform of the ready signal generation for a continuous input when NDLRB is 6 and CP prefix type is Normal, having FFT length as 128 and CP length as 10.

numHigh = FFT length + CP length = 128 +10 = 138 clock cycles.

numLow = Maximum FFT length + Maximum CP length - (numHigh) = 2048 + 160 - (138) = 2070 clock cycles.

This figure shows a Logic Analyzer waveform of the ready signal generation for a discrete input with 1 (high) for 16 clock cycles when NDLRB is 6 and CP prefix type is Normal, having FFT length as 128 and CP length as 10.

numHigh = (FFT length + CP length -1) * Maximum FFT length / FFT length + 1 = (128 +10 -1) * 16 + 1 = 2193 clock cycles.

numLow = Maximum FFT Length + Maximum CP Length - (numHigh) = 2048 + 160 - (2193) = 15 clock cycles.

This block supports windowed LTE transmission by implementing fractional cyclic prefix removal. Windowing reduces out-of-band emissions. A transmitter performs windowing by overlapping the tail of each OFDM symbol with the head of the next OFDM symbol. A receiver must avoid these overlapped samples in the FFT calculation. Fractional CP solves this problem by removing part of the CP at the start of a symbol and the remainder of the CP at the end of the symbol. Implementing a CP-fraction algorithm also makes the LTE OFDM Demodulator block less sensitive to timing offset.

The Cyclic prefix type parameter controls whether the block expects normal or extended CP. When the block operates at a maximum sample rate of 30.72 MHz, it assumes that each symbol is 2048 samples plus the cyclic prefix size associated with that rate. When using normal CP, the prefix of the first symbol in each slot has 160 samples, while subsequent symbols have a prefix of 144 samples. The extended CP has 512 samples.

When the block operates at sample rates with respect to the NDLRB value, for example, if the NDLRB is 6, the block receives 128 samples plus the cyclic prefix size associated with that rate. When using normal CP, the prefix of the first symbol in each slot has 10 samples, while subsequent symbols have a prefix of nine samples. The extended CP has 32 samples.

The block handles the CP in two stages. First, the block calculates the number of CP samples to remove, Nr, and removes those samples from the input samples. Next, it calculates the number of samples to shift, Ns, and shifts those samples to the end of OFDM symbol in the time domain. These two segments together make up the total cyclic prefix length, Ncp = Ns + Nr.

The CP fraction parameter controls how many samples the block removes at the beginning of the symbol. The block shifts the remainder of the cyclic prefix from the start of the symbol to the end of the symbol. The block quantizes CP fraction to fi(0,11,10). To achieve an integer number of samples, the block calculates Nr = floor (Ncp * CP fraction).

The Logic Analyzer waveform shows the control signals for the two stages of CP removal. The block is configured for a normal CP, so the CP of the first symbol is 160 samples. The CP for subsequent symbols is 144 samples. The CP fraction is 0.55.

In stage one, the block sets the internal valid signal to 0 (false) to exclude the first Nr samples of the symbol. For the first symbol, Nr = 88. Manipulation of the valid signal also excludes the final Ns samples, which are replaced by the shifted samples in the next stage. For the first symbol, Ns = 72. In stage two, the block writes the Ns samples to a RAM, and then reads and returns these samples at the end of the symbol. The block shifts the internal valid signal to include the shifted samples in their new location. The result is 2048 samples, properly aligned in the time domain in preparation for an FFT.

For the second symbol, with a cyclic prefix of 144 samples, Nr = 80 and Ns = 64.

For more information on LTE transmitter windowing, see the Algorithms section of the lteOFDMModulate (LTE Toolbox) function.

As the LTE OFDM Demodulator block uses a maximum FFT length of 2048. So, when the input samples corresponding to the actual FFT length are provided, the Sample Repeater block repeats the samples until it forms 2048 samples. For this operation, the block buffers the input samples first, and then repeats the samples based on the NDLRB value. This repetition mechanism helps avoid scaling at the FFT block input. For example, if the NDLRB is 6, each OFDM symbol consists of 128 samples. The block converts these 128 samples to 2048 samples by repeating them 16 times. After the block generates 2048 data samples, it sends data and valid signals to the next block.

Conventionally, receivers perform FFT shift in the frequency domain. However, this method requires memory and introduces latency related to the size of the FFT. Instead, a receiver can execute the same operation in the time domain using the frequency shifting property of Fourier transforms. Shifting a function in one domain corresponds to a multiplication by a complex exponential function in the other domain. To reduce hardware resources and latency, this block performs the FFT shift by multiplying the time-domain samples by a complex exponential function.

These equations describe an FFT shift. The equation for an N-point FFT is

For an FFT shift of N/2 carriers in either direction, substitute $$k=k-\frac{N}{2}$$, resulting in

This equation simplifies to

Since $${\displaystyle \sum _{n=0}^{N-1}x(n)e^{-\frac{j2\pi nk}{N}}}$$ is equivalent to $$F[x(n)]$$, and $$e^{j\pi }=-1$$, this equation simplifies to

The final equation shows that an FFT shift in the time domain simplifies to multiplication by (-1)ⁿ. Therefore, the block implements the FFT shift by multiplying the time-domain samples by either +1 or –1.

The output of the FFT shift subsystem is fed to an FFT block. The sample rate of the time-domain samples must be 30.72 MHz. The block calculates a 2048-point FFT for all NDLRB values.

The Divide butterfly outputs by two parameter controls whether the FFT implements an overall 1/N scale factor by dividing the output of each butterfly multiplication by two. This adjustment keeps the output of the FFT in the same amplitude range as its input. When you disable scaling (default), the block avoids overflow by increasing the word length by one bit after each butterfly multiplication.

This part of the algorithm selects the appropriate number of subcarriers based on the NDLRB. Out of 2048 subcarriers, the block selects the center 12xNDLRB subcarriers for output.

If the Remove DC subcarrier parameter is selected, the block excludes the DC subcarrier from the final resource grid output. The block excludes the DC subcarrier by setting the valid signal to 0 (false) for the center cycle of the output subcarriers.

For NDLRB 25, the block returns 12×25=300 resource grid samples. The block indicates the location of these output samples with the validOut signal set to 1 (true). The validOut signal is 0 (false) at the center of the output samples, to exclude the DC carrier.

This waveform shows the output when you set the Input data sample rate parameter to Use maximum input data sample rate and select an NDLRB of 25 with normal CP.

This waveform shows the output of the block when you set the Input data sample rate parameter to Match input data sample rate to NDLRB and select an NDLRB of 25 with normal CP. The block repeats four times at the input of FFT for computing 2048-point FFT. The actual FFT samples are taken for every one in four samples at the output of FFT. The block chooses the center (12×25 = 300) resource grid elements and outputs them along with valid signal.

The performance of the synthesized HDL code varies with your target and synthesis options. The input data type used for generating HDL code is fixdt(1,16,14).

This table shows the resource and performance data synthesis results when using the block with default configuration. The generated HDL targeted to an AMD^® Zynq^® XC7Z045I-FFG900-2L FPGA. The design achieves a clock frequency of 280 MHz.