LTE OFDM Modulator

An OFDM Symbol Formation subsystem calculates the number of active and inactive subcarriers and the number of CP samples. It generates a ready signal and subcarriers (active, inactive, and DC) for each OFDM symbol as per LTE standard.

The OFDM Symbol Formation subsystem calculates the number of active subcarriers based on the NDLRB value.

Number of active subcarriers = 12 x NDLRB

The number of inactive subcarriers is a difference of IFFT size and the number of active subcarriers. To save hardware resources by avoiding multiple IFFTs, the IFFT size is fixed to 2048.

Number of inactive subcarriers = 2048 — Number of active carriers

The block outputs a signal from ready port to indicate when the block is ready to accept input data. This signal depends on the valid input signal, NDLRB, CP type, and OFDM symbol number. The ready output signal is generated for one time step, and the valid input signal is checked for next time step. The block accepts the input data and the ready output signal remains high (1) until the OFDM symbol data is received. If the valid input is low (0), the ready signal extends until the valid input signal receives high (1). After receiving active subcarriers, the block sets the ready output signal to low (0) for a time period equal to the sum of the number of inactive subcarriers and the number of CP samples.

These figures show Logic Analyzer waveforms of the ready output signal for NDLRB values 25 and 100, respectively.

The IFFT block converts a frequency-domain signal to a time-domain signal. LTE supports six standard bandwidth options: 1.4 MHz, 3 MHz, 5 MHz, 10 MHz, 15 MHz, and 20 MHz. These bandwidth options require an FFT length of 128, 256, 512, 1024, and 2048, respectively. The block uses 2048 FFT length, which corresponds to the maximum bandwidth of LTE, that is 20-MHz. The FFT length of IFFT is configured to the highest FFT size to generate single hardware, which supports all LTE bandwidth options.

The Divide butterfly outputs by two parameter controls if the FFT implements an overall 1/N scale factor by dividing the output of each butterfly multiplication by two. This adjustment keeps the output of the IFFT in the same amplitude range as its input. When the Divide butterfly outputs by two parameter is cleared, the block avoids overflow by increasing the word length by 1 bit after each butterfly multiplication.

Conventionally, transceivers perform an FFT shift in the frequency domain. However, this method requires memory and introduces latency related to the size of the FFT. Instead, a transceiver can execute the same operation in the time domain using the frequency shifting property of Fourier transforms. Shifting a function in one domain corresponds to a multiplication by a complex exponential function in the other domain. To reduce hardware resources and latency, this block performs the FFT shift by multiplying the time-domain samples by a complex exponential function.

These equations describe an FFT shift. The equation for an N-point FFT is

For an FFT shift of N/2 carriers in either direction, substitute $$k=k-\frac{N}{2}$$, resulting in

This equation simplifies to

Since $${\displaystyle \sum _{n=0}^{N-1}x(n)e^{-\frac{j2\pi nk}{N}}}$$ is equivalent to $$F[x(n)]$$, and $$e^{j\pi }=-1$$, this equation simplifies to

The final equation shows that an FFT shift in the time domain simplifies to multiplication by (-1)ⁿ. Therefore, the block implements the FFT shift by multiplying the time-domain samples by either +1 or –1.

Cyclic prefix addition is a process of adding the last samples of an OFDM symbol as a prefix to each OFDM symbol. CP addition for an OFDM symbol with Nfft samples and CP samples N_CP is shown in this figure.

The LTE OFDM Modulator block uses FFT size of 2048 for all NDLRB resources to avoid multiple IFFTs. The block uses CP values corresponding to NDLRB 100.

The Cyclic prefix type parameter controls whether the block expects a normal or an extended CP. The block requires the input to maintain a sample rate of 30.72 MHz. It assumes that each symbol is 2048 samples plus the cyclic prefix size associated with the rate. When using a normal CP, the prefix of the first symbol in each slot has 160 samples, while each subsequent symbol contains a prefix of 144 samples. When using an extended CP, all symbols contain 512 samples. For more information about the cyclic prefix length (in samples) of each OFDM symbol in a subframe, see the lteOFDMModulate (LTE Toolbox) function.

Windowing reduces the spectral regrowth, or adjacent channel leakage ratio (ACLR), of an OFDM signal. The feature is optional. To enable windowing, select the Windowing parameter.

For more information about windowing, see the lteOFDMModulate (LTE Toolbox) function.

This block generates the output data at a sample rate of 30.72 MHz by using the maximum output data sample rate or output data sample rate with the specified NDLRB.

This figure shows a Logic Analyzer waveform of the output data when you set the Output data sample rate parameter to Use maximum output data sample rate.

This figure shows a Logic Analyzer waveform of the output data when you set the Output data sample rate parameter to Match output data sample rate to NDLRB parameter. For NDLRB value 25, the output sample rate is 7.68 MHz, and the block returns valid output data at every fourth cycle.

The performance of the synthesized HDL code varies with your target and synthesis options. The input data type used for generating HDL code is fixdt(1,16,14).

This table shows the resource and performance data synthesis results when using the block with default configuration. The generated HDL targeted to an AMD^® Zynq^® XC7Z045I-FFG900-2L FPGA. The design achieves a clock frequency of 247 MHz.