ip core generation stuck at hdl code generation step

Question

Prashanthi Pathipati 2023-5-15

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此问题的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/1963734-ip-core-generation-stuck-at-hdl-code-generation-step

编辑： Prashanthi Pathipati 2023-7-31

i have to convert function to ip using hdl coder but while converting it stuck at HDL code generation

1.the ouput Q port has 12*12 matrix, so in HDL code genetaion i have enabled frame to sample conversion

still am facing issues but i opted Generic ASIC/FPGA it generated a .v (verilog) file

could please help me out where am going wrong or do i have enable any other things

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Answer 1

Kiran Kintali 2023-5-15

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https://ww2.mathworks.cn/matlabcentral/answers/1963734-ip-core-generation-stuck-at-hdl-code-generation-step#answer_1235664

Would you be able to share the MATLAB Code and the Project file?

Please reach out to tech support for help.

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Kiran Kintali 2023-5-25

编辑：Kiran Kintali 2023-5-25

thank you for the submission.

can you remove these issues with get6.m?

The design (DUT/Chip) has inputs but they are unused. There are several other issues in the code that need to be resolved prior to HDL Code generation.

>> mlint get6

L 1 (C 49-57): Input argument might be unused. Consider replacing the argument with ~ instead.

L 1 (C 59-66): Input argument might be unused. Consider replacing the argument with ~ instead.

L 3 (C 1-7): The preallocated value assigned to variable might be unused.

L 4 (C 1-5): The preallocated value assigned to variable might be unused.

L 30 (C 1-6): The preallocated value assigned to variable might be unused.

L 31 (C 1-8): The preallocated value assigned to variable might be unused.

L 32 (C 1-4): The preallocated value assigned to variable might be unused.

L 35 (C 1): The preallocated value assigned to variable might be unused.

L 36 (C 1): The preallocated value assigned to variable might be unused.

L 37 (C 1-12): The preallocated value assigned to variable might be unused.

L 40 (C 1-14): The preallocated value assigned to variable might be unused.

L 41 (C 1-15): The preallocated value assigned to variable might be unused.

L 44 (C 1-11): The preallocated value assigned to variable might be unused.

L 47 (C 1-2): The preallocated value assigned to variable might be unused.

L 49 (C 1-5): The preallocated value assigned to variable might be unused.

L 50 (C 1): Value assigned to variable might be unused.

L 57 (C 1-9): The preallocated value assigned to variable might be unused.

L 58 (C 1-11): The preallocated value assigned to variable might be unused.

L 59 (C 1-3): The preallocated value assigned to variable might be unused.

L 60 (C 1-3): The preallocated value assigned to variable might be unused.

L 61 (C 1-3): The preallocated value assigned to variable might be unused.

L 64 (C 10): Add a semicolon after the statement to hide the output (in a function).

L 68 (C 1): The preallocated value assigned to variable might be unused.

L 70 (C 5-6): Value assigned to variable might be unused.

L 73 (C 5-10): The preallocated value assigned to variable might be unused.

L 74 (C 5-10): The preallocated value assigned to variable might be unused.

L 75 (C 5-11): The preallocated value assigned to variable might be unused.

L 77 (C 5-14): The preallocated value assigned to variable might be unused.

L 78 (C 5-15): Value assigned to variable might be unused.

L 89 (C 5-8): Value assigned to variable might be unused.

L 90 (C 5-19): The preallocated value assigned to variable might be unused.

L 91 (C 5-18): The preallocated value assigned to variable might be unused.

L 92 (C 5-18): The preallocated value assigned to variable might be unused.

L 94 (C 5-12): The preallocated value assigned to variable might be unused.

L 95 (C 5-10): The preallocated value assigned to variable might be unused.

L 96 (C 5-11): The preallocated value assigned to variable might be unused.

L 113 (C 11-12): Value assigned to variable might be unused.

L 117 (C 11-12): This keyword might not be aligned with its matching END on line 329.

L 118 (C 13-14): This keyword might not be aligned with its matching END on line 228.

L 123 (C 15-16): Value assigned to variable might be unused.

L 128 (C 15-16): This keyword might not be aligned with its matching END on line 227.

L 131 (C 17-24): The preallocated value assigned to variable might be unused.

L 178 (C 19-25): The preallocated value assigned to variable might be unused.

L 195 (C 18-19): This keyword might not be aligned with its matching END on line 222.

L 207 (C 19-25): The preallocated value assigned to variable might be unused.

L 208 (C 22): Loop index 'j' is changed inside of a FOR loop.

L 237 (C 28-35): The preallocated value assigned to variable might be unused.

L 280 (C 18-24): The preallocated value assigned to variable might be unused.

L 307 (C 21-27): The preallocated value assigned to variable might be unused.

L 308 (C 25): Loop index 'j' is changed inside of a FOR loop.

L 309 (C 23-24): This keyword might not be aligned with its matching END on line 320.

L 416 (C 9-10): Value assigned to variable might be unused.

L 418 (C 11-12): This keyword might not be aligned with its matching END on line 420.

L 419 (C 17-21): Value assigned to variable might be unused.

>>

Angela Cuadros Castiblanco 2023-5-31

Hello Prashanthi,

In general, matrix ports at the DUT interface are not supported in the IP core generation workflow unless Frame to Sample conversion is enabled. However, generating an IP core using frame to sample conversion is not supported for the MATLAB to HDL workflow as specified in the limitations listed in:

https://www.mathworks.com/help/hdlcoder/ug/frame-to-sample-or-pixel-conversion-to-target-stream-based-hardware.html#mw_0a9f7d35-7b4f-4b63-a3cb-a30506f97a26

If you have access to Simulink, you can try generating an IP core from a Simulink model with a MATLAB function block, for an example see:

https://www.mathworks.com/help/hdlcoder/ug/deploy-a-frame-based-model-with-AXI4-Stream-interfaces.html

Alternatively, you can manually serialize the output of your design and map the scalar ports of the streaming output to AXI4-Stream interfaces and generate an IP core. For an example see:

mlhdlc_demo_setup('heq')

Hope that helps!

Prashanthi Pathipati 2023-7-31

编辑：Prashanthi Pathipati 2023-7-31

the problem of generating 2-D matrix as output not relsoved,so i have decided them not include them in output and i have generated an IP with axi interface.

the problem am facing when i export the IP to vivado

1.In simulation part am able to observe the desirble output values but its not synthesizable .

2.when i observed the verilog code ,the whole code is in initial block ,as in verilog initial block is ignored in synthesis

i have changed initial block to always block and sensitive list as clock still no use.

would please suggest me a way to work on this problem like how t make the ip systhesizable or the code as systhesizable.

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