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HDL Coder to / downto order
The control is now available starting R2023b release for boolean arrays. https://www.mathworks.com/help/releases/R2023b/hdlc...

1 year 前 | 0

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Can I control the HDL to/downto designation used for arrays during HDL generation?
The control is available starting R2023b release for boolean arrays. https://www.mathworks.com/help/releases/R2023b/hdlcoder...

1 year 前 | 0

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HDL-Coder: Vivado gives errors creating bitstream due to disconnected URAM cascade inputs
>> Using Simulink/HDL Coder, I've created a system that works "just great" Glad to hear it. The error you describe in the mess...

1 year 前 | 0

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why matlab throws an error while doing "build model" in soc builder? the error "version 2022.2 of tool xilinx vivado is not supported in hdl workflow advisor. How to fix it?
Each release HDL Coder is tested with specific versions of EDA tools. R2023a release is officially tested with the following v...

1 year 前 | 0

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Represent std_logic_vector in Simulink
HDL Coder supports fixed point data types with integer lengths ranging from 1 to 128 bits. During the HDL code generation proce...

1 year 前 | 0

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matlab function example or suggestion, so that it will generate hdl code in verilog using non blocking assignments
This link has several examples that generate HDL from MATLAB designs. https://www.mathworks.com/matlabcentral/fileexchange/5009...

1 year 前 | 0

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give error in converting the simulation into hdl code
This link provides design patterns of MATLAB Code and Simulink models that let you generate HDL Code. https://www.mathworks.c...

1 year 前 | 0

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HDL Coder can not generate the code
This error is unexpected from HDL Coder that happens when the DUT / referenced model has zero input and output ports. Such subsy...

1 year 前 | 0

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how to generate hdl code for the cyclic prefix removal part of NPARCH fromats using the hdl simulink block set
You need to partition your code into design and testbench files and use MATLAB HDL Coder workflow Try this command to see an ex...

1 year 前 | 0

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Comparison 4 numbers without using if action in simulink
https://www.mathworks.com/help/dsp/ref/maximum.html In case you are using Simulink and have access to DSP System Toolbox, max b...

1 year 前 | 1

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How to solve this error?
This is an internal and not user facing error. Please reach out to tech support to report the issue and potential workaround.

1 year 前 | 1

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hdl generated ip stuck at synthesis part in vivado
Consider using resource report to make sure you are at a high level within the limits of the FPGA resources. sfir_fixed makehd...

1 year 前 | 0

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How to initialize DDR External memory, such as InstructionData and WeightData unused dlhdl.Workflow deploy() function
https://www.mathworks.com/help/releases/R2023a/deep-learning-hdl/ug/deploy-simple-adder-network-by-using-MATLAB-deployment-uti...

1 year 前 | 0

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Simscape HDL Workflow Simulation Stop Time
Can you share the model if you can that causes the error or reach out to technical support for futher assistance? Thanks

1 year 前 | 0

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I'm trying to implement a method used by Mr. Jeff Miller in a Matlab training session entitled "Fixed Point Made Easy," and had a question regarding his use of look-up tables
Can you share the training material and models you are referring to? Looking at the picture you attached the two LUTs are not t...

1 year 前 | 0

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Offset binary in Simulink HDL
a = fi(-pi, 1, 6, 0); msb = getmsb(a); c = bitcmp(msb); You can write a MATLAB function block with getmsb and bitcmp functi...

1 year 前 | 0

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I have generated HDL IP in matlab but not able to synthesize the IP In Vivado
https://www.mathworks.com/help/hdlcoder/examples.html?category=hdl-code-generation-from-matlab You can check demo examples ...

1 year 前 | 1

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CONVOLUTION process with the HDL simulink blocks, does not giving the similar output for the MATLAB script output (highvariations between the simulink and script output))
Caused by: Error using slhdlcoder.SimulinkConnection/initModel Error evaluating parameter 'X' in 'subsystem_simlunik_c...

1 year 前 | 0

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Unable to map lookup tables to RAM in HDL coder
Can you share a sample model with your configuration settings and desired synthesis results? All floating point operator level ...

1 year 前 | 0

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Kalman filter for FPGA in HDL Coder?
You need to break the MATLAB code into design and testbench and use MATLAB to HDL code advisor. See the sample example below. ...

1 year 前 | 0

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Unable to find an installed compiler.
If mex -setup points to a valid compiler; floating point to fixed point conversion should proceed without any errors. if this i...

1 year 前 | 0

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Is the creation of a test bench possible, without the use of the HDL coder software?
https://www.mathworks.com/products/matlab-test.html MATLAB Test provides tools for developing, executing, measuring, and managi...

1 year 前 | 0

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Do not undertand this error of missing license which contradicts 'license checkout statement'
... so that i can use it to generate HDL code for Microsemi Libero FPGA software ... You can try the examples in this page h...

1 year 前 | 0

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Please give latest version numbers of the following modules
Installing MATLAB and typing ver displays the latest version information https://www.mathworks.com/help/matlab/ref/ver.html ve...

1 year 前 | 0

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HDL user-defined block RAM
This usually implies generated HDL didn't meet the original MATLAB or Simulink results. Please reach out to technical support ...

1 year 前 | 0

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Is it possible to generate a VHDL File from a MATLAB Function that only contains one (clocked) process?
The current code style is driven by synthesis best practices. Please reach to technical support for additional customization r...

1 year 前 | 0

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HDL-Coder: initialization of internal VHDL-signals
All HDL Coder generated signals are fully initialized or driven with valid logic. Lack of valid drivers to signals is consid...

1 year 前 | 0

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How to create VHDL code of a Neural Network block created through GENSIM command ?
This example shows how to convert a neural network regression model (created using gensim) to HDL Code. https://www.mathworks...

1 year 前 | 0

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FPGA Synthesis and Analysis HDL coder
There are many reasons for the synthesis step to be taking a long time. If the generated HDL does not fit on the FPGA or very c...

1 year 前 | 0

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how can i use contiuous time integrator in hdl coder?
HDL Coder only generates code from discrete blocks. Continuous blocks are not supported. Consider using discrete time integrat...

1 year 前 | 0