What Is Simulink Design Verifier?

Simulink Design Verifier™ uses formal methods to identify design errors, verify requirements, and automatically generate test cases for Simulink^® and Stateflow^® models. Detect issues such as integer overflow, division by zero, dead logic, array access violations, and floating-point errors before deployment. Improve model coverage and code coverage, including MC/DC coverage, with automated test vector generation. Generate counterexamples for requirements violations, extend existing test suites, perform back-to-back testing, and support verification workflows for safety-critical systems. Accelerate analysis with multicore processing and gain greater confidence before code generation and implementation.