Integrated Circuit (IC) Design engineers use MATLAB and Simulink to enhance and improve the design, verification, and prototyping of integrated circuits throughout development.
With MATLAB and Simulink, you can:
- Use Model-Based Design to enhance architectural exploration, enable early verification, accelerate the verification process, and reduce development time and costs
- Generate synthesizable RTL code and C/C++, HDL, System C, and IBIS-AMI testbenches and models to accelerate prototyping, implementation, and verification
- Reuse existing MATLAB and Simulink models within Electronic Design Automation (EDA) workflows, leveraging them as golden reference models, stimuli generators, and validated testbenches
- Improve the efficiency of analog and mixed-signal designs with automation, advanced reporting, curve fitting, and AI
NEW
Blog
Semiconductor Design and Verification
Streamline Architectural exploration, optimize post-processing of simulation and start verification early with MATLAB and Simulink
Streamline Architectural Exploration
You can use MATLAB to analyze high-level system architectures, such as deciding between a second- or third-order sigma-delta modulator or selecting the best phase-locked loop (PLL) type. As integration and advanced process nodes increase the complexity of analog-digital interactions, you may encounter challenges in system modeling, verification, and noise analysis. MATLAB and Simulink enable you to model analog circuits, digital controllers, FSMs, and DSP elements together, facilitating early what-if analysis and verification. You can reuse these models in EDA flows, promoting a shift-left approach. Products like Mixed-Signal Blockset let you explore the design space and perform static analysis of PLLs, helping you identify the best starting point for your designs. Products like SerDes Toolbox let you model, analyze, and simulate SerDes systems and automatically generate dual PAMn IBIS-AMI models.
Analyze and Optimize Designs
MATLAB and Simulink products let you analyze and optimize mixed-signal IC designs. You can import and analyze large simulation results from Cadence® Virtuoso® ADE Explorer and Assembler with MATLAB, identify data trends, generate reports, and optimize designs. The SerDes Designer app lets you design wired communication links using statistical analysis and explore equalizer configurations to enhance channel performance. You can conduct experiments on multiple parameters, extract design metrics, and visualize waveforms for high-speed links such as DDR5, PCIe, and PAM. Also, you can automate simulations, analyze data, and create visualizations directly from the MATLAB command line.
Integrate with EDA Design Workflows
By generating portable, synthesizable Verilog®, SystemVerilog, and VHDL® code from MATLAB functions, Simulink models, and Stateflow charts, you can conduct early RTL analyses and optimization, including Power-Performance-Area (PPA) assessments. This capability—along with optimizing RTL code for speed and area, highlighting critical paths, and obtaining resource estimates—enables you to shift-left the design and verification cycle. A workflow advisor automates prototyping on AMD®, Intel®, and Microchip boards and generates IP cores for ASIC and FPGA workflows. Traceability ensures code verification for high-integrity applications meeting standards like DO-254.
Videos
- From MATLAB to Optimized RTL in Minutes with HDL Coder and Cadence Stratus HLS (42:01)
- From Algorithms to FPGA / ASIC Implementation with MATLAB and Simulink (57:05)
- Innovative GSPS Signal Processing Solution with MATLAB Simulink for FPGA SoC (17:11)
- Developing Next-Generation Lidar with Model-Based Design (12:40)
Customer Stories
- Renesas Designs and Implements Image Processing IP Core for ASICs with Model-Based Design
- Rambus Develops DSP Blocks for ASICs Using High-Level Synthesis with HDL Coder
- Generating Space-Compliant HDL Code for a UHF Satellite Communications Processor at Thales Alenia Space
- LG Electronics Develops Smart Headlamp with a Rapid Prototyping Workflow
- Semtech Speeds Development of Digital Receiver FPGAs and ASICs
Start Verification Early
By starting at higher abstraction levels with MATLAB and Simulink, you can develop testbenches and algorithmic models closely aligned with system requirements. SystemVerilog DPI-C models generated from MATLAB and Simulink facilitate building RTL verification environments, such as Universal Verification Methodology (UVM), or test harnesses for SPICE® models. This enables early verification, reusing system-level models validated by the architecture team. Once the design is ready, you can verify your algorithms via cosimulation, with testbenches in MATLAB or Simulink and designs in simulators like Cadence® Xcelium™, AMS, Spectre, Synopsys® VCS®, Siemens® Questa™, or the AMD® Vivado® simulator. This approach can significantly enhance productivity and reduce verification times.
Customer Stories
- NXP Semiconductors: Environment-in-the-Loop Verification of Automotive Radar IC Designs
STMicroelectronics: Reuse of Simulink Components within Chip-Level Design and Verification Environments - Marvell Semiconductor, SeriaLink Systems, and MathWorks (DesignCon 2022): Validation Shift-Left: Enabling Early SerDes Mixed-Signal Validation
- Allegro Microsystems: Applying Model-Based Verification in Automotive ASIC Development
- ROHM Semiconductor: Improving the Efficiency of IC Development with Model-Based Design
