Synthesize Generated HDL Code from MATLAB Algorithms

Once you have generated HDL code from your compatible MATLAB® algorithm with HDL Coder™, you can use HDL Coder to optimize your design for speed and area, and to facilitate FPGA synthesis, implementation, and programming.

This example shows how to synthesize generated HDL code for a MATLAB algorithm. In this example, you use a MATLAB algorithm that models a simple up counter. This counter is compatible with HDL code generation. To learn more about how to make a MATLAB algorithm compatible with HDL code generation, see Create HDL- or HLS-Compatible MATLAB Algorithms.

In this example, you:

  1. Set up a third-party synthesis tool.

  2. Create a MATLAB HDL Coder project.

  3. Generate HDL code from the MATLAB algorithm.

  4. Synthesize the generated HDL code using a third-party synthesis tool and analyze the result.

To synthesize HDL code from a Simulink model, see HDL Code Generation and FPGA Synthesis from Simulink Model.

Set Up Synthesis Tool Path

First, set up a third-party synthesis tool by using hdlsetuptoolpath to define the path to the third-party synthesis tool executable. This example uses AMD® Vivado®.

  1. Install AMD Vivado. To check your installation, launch AMD Vivado by entering !vivado in the MATLAB Command Window. If you open AMD Vivado to check your installation, close the application without saving.

  2. Use hdlsetuptoolpath to set up your third-party synthesis tool with MATLAB. In the MATLAB Command Window, use this command, and replace the ToolName and ToolPath with your synthesis tool and synthesis tool installation path:

hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath',...
 'C:\Xilinx\Vivado\2024.1\bin\vivado.bat');

For more information on supported third-party tools and hardware, see HDL Language Support and Supported Third-Party Tools and Hardware.

MATLAB Counter Algorithm

Open Live Script

Open this example to obtain the MATLAB counter function and test bench for this tutorial.

open mlhdlc_counter
open mlhdlc_counter_tb

The MATLAB function mlhdlc_counter is a model of a 4-bit synchronous up counter. When the input argument, enable_ctr, is a nonzero value, the persistent variable, count_val, increases by one. The value of count_val increases by one until the count reaches 15. Then the counter returns to zero. To learn more about this function and the associated test bench, see Create HDL- or HLS-Compatible MATLAB Algorithms.

Create a MATLAB HDL Coder Project

To create a MATLAB HDL Coder project:

  1. In the MATLAB Editor, in the Apps tab, select HDL Coder. In the MATLAB HDL Coder Project window, set Name to mlhdlc_counter. Set Location to the current working directory. HDL Coder creates the mlhdlc_counter.prj project in the specified directory.

  2. In the HDL Code Generation window, in the MATLAB Function section, click Add MATLAB function and select the function file for the up counter algorithm, mlhdlc_counter.m. In the MATLAB Test Bench section, click Add files and add the MATLAB test bench, mlhdlc_counter_tb.m.

    You must add a MATLAB test bench unless the design does not need fixed-point conversion and you do not want to generate a register transfer level test bench.

    Note

    Add only the top-level MATLAB function. Do not use spaces in file names or paths to prevent code generation failures.

  3. In the MATLAB Function section, click Autodefine types and then click Run. HDL Coder infers the input types by executing the MATLAB test bench. Click Use These Types to use the recommended types for the MATLAB design. If you do not add a test bench, you must define the inputs to the top-level MATLAB function. For more information, see Specify Properties of Entry-Point Function Inputs.

  4. Click Workflow Advisor.

Default view on launching the MATLAB HDL Coder App. The interface includes sections for adding a MATLAB function, a MATLAB test bench, auto-defining types, and starting the workflow advisor.

Generate HDL Code

Use the Workflow Advisor to generate HDL code for FPGA synthesis:

  1. In the Workflow Advisor, click the Select Code Generation Target task.

  2. Set Synthesis tool to Xilinx Vivado.

  3. Set Target Frequency (MHz) to 50.

  4. Right-click HDL Code Generation and select Run to Selected Task.

View of the Select Code Generation Target step in the HDL Workflow Advisor. The Workflow is set to Generic ASIC/FPGA, the Synthesis tool is set to Xilinx Vivado, and the Target frequency is set to 50 MHz.

Perform FPGA Synthesis and Analysis

Use the Workflow Advisor to facilitate synthesis, implementation, and analyze the generated code.

In the Workflow Advisor, right-click the Synthesis and Analysis > Run Implementation task and select Run to Selected Task.

HDL Coder runs these tasks to generate HDL code for the algorithm:

  1. In the Create Project task, the third-party synthesis tool creates a synthesis project for the HDL code.

  2. In the Run Synthesis task, HDL Coder launches the third-party synthesis tool in the background. The third-party synthesis tool opens the synthesis project, compiles the HDL code, synthesizes the design, and generates the netlists, area, and timing reports.

  3. In the Run Implementation task, HDL Coder launches the third-party synthesis tool in the background. The third-party synthesis tool places and routes the design for the specified hardware and generates pre- and post-route timing information for critical path analysis.

Click the Run Implementation task. In the bottom right pane, scroll to the top and click post_synth_report.html to view the place and route report.

Table from the synthesis and implementation report detailing the resource utilization and timing summary for the synthesized MATLAB algorithm. The table includes data on CLB LUTs, CLB Registers, DSPs, Block RAM, and URAM usage, as well as timing properties such as the timing requirement, data path delay, slack, and clock frequency.

The Resource Summary section shows that 0.02% of the FPGA is in use.

In the Timing Summary section, a positive slack indicates that the data propagates through a path faster than required, with time left over.

If your design does not meet timing or resource constraints, use speed and area optimizations in HDL Coder to meet these requirements, respectively. To learn more, see Introduction to Optimizations in HDL Coder.

See Also

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