HDL 代码生成
为被控对象模型生成 HDL 代码以部署到目标硬件平台上。使用 sschdladvisor 函数生成称为 HDL 实现模型的 HDL 兼容状态空间模型。您可以使用 HDL Coder™ 为此模型生成代码。
在生成代码之前，您可以指定 single 或 double 浮点数据类型，或指定 fixed-point 数据类型来执行 HDL 算法的矩阵计算。您可以生成逻辑来验证生成的 HDL 实现模型是否在功能上等效于原始 Simscape™ 模型。对于此逻辑，您还可以指定数值正确性的容差值。
函数
sschdladvisor | Open Simscape HDL Workflow Advisor |
hdladvisor | Display HDL Workflow Advisor |
hdlsetuptoolpath | Set up system environment to access FPGA synthesis software |
makehdl | Generate HDL RTL code from model, subsystem, or model reference |
主题
- Generate HDL Code for Simscape Models
Generate HDL code from Simscape switched linear models.
- Generate HDL Code for FPGA Platforms from Simscape Models (Simscape)
Learn how to convert Simscape models to HDL Code for FPGA Deployment.
- Generate Optimized HDL Implementation Model from Simscape
Optimize area and timing of HDL implementation model generated from Simscape by using HDL Coder optimizations.
- Validate HDL Implementation Model to Simscape Algorithm
Validate and resolve simulation mismatch between Simscape algorithm and HDL implementation model.
- Improve FPGA Sampling Frequency of HDL Implementation Model Generated from Simscape Algorithm
Oversampling in generated HDL implementation model, and relation between model sample time and sample time of original Simscape algorithm.
- Generate HDL Code for Two-Speed Transmission Model Containing Mode Charts
Generate HDL code and synthesize the results for a two-speed transmission model with braking that contains mode charts.
- Synthesis Results for Simscape Hardware-in-the-Loop Workflow
Access synthesis results for Simscape hardware-in-the-loop workflow example models.
