HDL Test Bench

Generate a test bench that verifies generated HDL code against test vectors from Simulink^®

When you generate HDL code, you can optionally generate an HDL test bench that verifies the generated HDL DUT against test vectors saved from your Simulink model.

Functions

makehdltb Generate HDL test bench from model or subsystem

Topics

Test Bench Generation
Learn how HDL test bench generation works.
Choose a Test Bench for Generated HDL Code
Select a generated test bench.
Verify Generated Code Using HDL Test Bench from Configuration Parameters
Generate a HDL test bench to simulate and verify the generated HDL code for your design.
Verify Generated Code Using HDL Test Bench at Command Line
Learn how to generate a HDL test bench to verify the VHDL, Verilog or SystemVerilog Code.