HDL 测试平台生成

R2026b

生成测试平台，以基于 MATLAB^® 或 Simulink^® 的测试向量验证生成的 HDL 代码

生成 HDL 代码时，您可以选择生成 HDL 测试平台，以基于 Simulink 模型或 MATLAB 代码保存的测试向量验证生成的 HDL DUT。您还可以从生成的测试平台运行的测试收集代码覆盖率信息。有关如何选择和运行测试平台的详细信息，请参阅Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor。

函数

makehdltb Generate HDL test bench from model or subsystem

模型设置

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测试平台

仿真工具	Simulator to use to run generated test benches
HDL 代码覆盖率	Enable HDL code coverage flags in generated simulator scripts
HDL 测试平台	Enable HDL test bench generation
联合仿真模型	Generate cosimulation model
SystemVerilog DPI 测试平台	Enable SystemVerilog DPI test bench generation
测试平台名称后缀	Suffix to append to test bench name
强制时钟	Whether test bench forces clock input signals
时钟高电平时间(ns)	Period during which test bench drives clock input signals high
时钟低电平时间(ns)	Period during which test bench drives clock input signals low
保持时间(ns)	Hold time for input signals and forced reset input signals
强制时钟使能	Whether test bench forces clock enable input signals
时钟使能延迟(以时钟周期为单位)	Elapsed time between deassertion of reset and assertion of clock enable
强制复位	Whether test bench forces reset input signals
复位长度(以时钟周期为单位)	Length of time during which reset is asserted
保持采样之间的输入数据	Hold data values for subrate signals for number of base-rate clock cycles in subrate sample period
初始化测试平台输入	Specify initial value driven on test bench inputs before data is asserted to DUT
多文件测试平台	Divide generated test bench into helper functions, data, and HDL test bench code files
测试平台数据文件名后缀	Suffix to append to test bench data file name when generating multi-file test bench
测试平台参考后缀	Suffix to append to names of reference signals generated in test bench code
使用文件 I/O 读取/写入测试平台数据	Create data files for reading and writing test bench input and output data
忽略输出数据检查(采样数)	Number of samples during which output data checking is suppressed
浮点容差检查依据	Check for errors in floating-point library based on relative or ULP errors
容差值	Floating-point tolerance value
仿真库路径	Path of compiled Altera or AMD simulation libraries

主题

验证基础知识

Choose a Test Bench for Generated HDL Code
Select a generated test bench.
Generated Model and Validation Model
The generated model is a model created during HDL code generation that shows the HDL implementation architecture and includes latency.

MATLAB 代码的 HDL 测试平台

Verify Code with HDL Test Bench
Simulate the generated HDL design under test (DUT) with test vectors from the test bench using the specified simulation tool.
Using Test Benches With HDL and HLS Code Generation
MATLAB test bench requirements and best practices for HDL and High-Level Synthesis (HLS) code generation.
Test Bench Generation
HDL Coder™ writes the DUT stimulus and reference data from your MATLAB or Simulink simulation to data files (.dat).
Specify Test Bench Clock Enable Toggle Rate
Specify test bench clock enable toggle rate.

Simulink 模型的 HDL 测试平台

Verify Generated HDL Code from Simulink Model
Generate an HDL test bench to verify the VHDL^® or Verilog^® Code.
Verify Generated Code Using HDL Test Bench at Command Line
Learn how to generate an HDL test bench to verify the VHDL, Verilog or SystemVerilog Code.
Test Bench Generation
Learn how HDL test bench generation works.
Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor
Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.
测试平台模块限制
确定哪些模块不支持直接连接到 DUT 进行测试平台生成。

疑难解答

Resolve Index Errors During HDL Simulation

Troubleshoot index errors during HDL code simulation.

精选示例

Locate Numeric Differences After Speed Optimization

Learn about numeric differences between original and generated models.

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