Memory Traffic Generator
R2026bGenerate traffic towards memory controller
Libraries:
SoC Blockset for AMD /
SoC System Simulation /
Memory
HDL Coder /
SoC System Simulation /
Memory
Description
When connected to a memory controller, the Memory Traffic Generator block generates read or write requests to the memory, acting as an initiator. Use this block to model the impact that a master’s memory accesses has on your algorithm without explicitly simulating the behavior of that master. You can also use the Memory Traffic Generator block to characterize performance of your memory subsystem under varying levels of memory access contention.
Note
To model memory contention, the Memory Traffic Generator block gains memory access, competes in arbitration, and releases access. The Memory Traffic Generator block does not actively read or write from memory.
Parameters
Extended Capabilities
Version History
Introduced in R2019aSee Also
AXI4-Stream to Software (SoC Blockset) | Software to AXI4-Stream (SoC Blockset) | AXI4 Video Frame Buffer (SoC Blockset) | AXI4 Random Access Memory (SoC Blockset) | Register Channel (SoC Blockset)