内存
R2026b设计和开发 SoC 应用的共享内存和数据寄存器组件
SoC Blockset™ for AMD 支持在 Simulink® 中仿真和评估共享内存事务处理。通过使用逻辑分析仪，在部署到 SoC 器件之前可视化仿真后性能和带宽度量。
模块
 | AXI4 Random Access Memory | Model random access through external memory (自 R2022b 起) |
 | AXI4-Stream to Software | Stream AXI4 data from FPGA to software (自 R2022b 起) |
 | Software to AXI4-Stream | Stream AXI4 data from software to FPGA (自 R2022b 起) |
 | AXI4 Video Frame Buffer | Model connection between two hardware algorithms through external memory (自 R2022b 起) |
 | Memory Traffic Generator | Generate traffic towards memory controller |
 | Register Channel | Timing model for transfer of register values |
 | Interrupt Channel | Send interrupt to processor from hardware |
 | AXI4 Master Sink | Receive random access memory data |
 | AXI4 Master Source | Generate random access memory data |
 | Stream Data Sink | Receive continuous stream data |
 | Stream Data Source | Generate continuous stream data |
 | IP Core Register Read | Model register writes from software to hardware |
 | SoC Bus Selector | Convert bus to control signals |
 | SoC Bus Creator | Convert control signals to bus |
 | Stream FIFO | Control backpressure between hardware logic and upstream data interface |
 | Stream Connector | Connect two IPs with data streaming interfaces |
 | Register Read | Read data from a register region on the specified IP core |
 | Register Write | Write data to a register region on the specified IP core |
 | Stream Read | Stream data from shared memory to processor algorithms |
 | Stream Write | Stream data from processor algorithms to shared memory |
 | Video Stream FIFO | Control backpressure between hardware logic and upstream video interface |
 | Video Stream Connector | Connect two IPs with video streaming interfaces |
App
| 逻辑分析仪 | Visualize, measure, and analyze transitions and states over time |
工具
| 性能报告 | Display performance and core usage metrics after model simulation or execution on SoC device |
主题
设计
- Memory and Register Data Transfers (SoC Blockset)
Introduction to memory and register transfers. - External Memory Channel Protocols (SoC Blockset)
Supported memory channel protocols and control signals. - AXI4-Stream Interface (SoC Blockset)
How to design your model for AXI4-Stream vector or scalar interface generation. - Simplified AXI4 Master Interface (SoC Blockset)
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces. - AXI4-Stream Video Interface (SoC Blockset)
How to design your model for IP core generation with AXI4-stream video interfaces.
仿真
- Simulation Diagnostics (SoC Blockset)
SoC Blockset for AMD enables simulation and evaluation of memory transactions in Simulink without the need to deploy a model to an SoC device. - Simulation Performance Tips (SoC Blockset)
Suggestions for enhancing simulation performance of SoC models. - Simulation Performance Plots (SoC Blockset)
SoC Blockset for AMD enables post-simulation analysis of memory diagnostic data.
测量
- Memory Performance Information from FPGA Execution (SoC Blockset)
Obtain memory interconnect traffic information from a design running on FPGA.
精选示例
Random Access of External Memory Using Altera Devices
Model external memory accesses from an FPGA for rotating an ASCII art image. Many applications require the FPGA to access memory in a random fashion as per the requirements of algorithm. You learn how to design memory address generation along with other AXI4 master signals to read and write specific regions of memory. You simulate, implement, and verify your design on hardware.
