片上系统 (SoC)
R2026b创建应用的 SoC 或专用 SoC Simulink® 模型。使用预配置模型模板或遵循 SoC 模型规范。模型模板提供设计模式并实现用于创建 SoC 模型的最佳做法。建议的工作流演示了将处理器软件、用户指定的可编程逻辑、共享内存系统和片上外设组合起来以创建一个应用的 SoC 模型的过程。使用分析函数和工具估计应用使用的资源。比较不同架构，以了解在处理器软件和可编程逻辑之间分区的设计权衡。
使用 Altera® 设计工具为 SoC、MCU、ASIC 和 FPGA 导出参考设计。自动生成硬件和软件代码，然后使用 SoC 构建器工具在 SoC 器件上执行应用。代码生成需要 HDL Coder™ 产品、Embedded Coder® 产品或同时需要两者。
App
| 嵌入式 Linux 资源管理器 | Connect to hardware, monitor resources, and control applications running embedded Linux (自 R2023a 起) |
工具
| SoC 构建器 | Build, load, and execute SoC model on SoC, FPGA, and MCU boards |
函数
socModelAnalyzer | Estimate number of operations in Simulink model |
socFunctionAnalyzer | Estimate number of operations in MATLAB function |
socAlgorithmAnalyzerReport | Open algorithm analysis report |
socExportReferenceDesign | Export custom reference design for HDL Workflow Advisor |
socTaskSchedulability | Determine whether set of tasks can be scheduled for specified core assignments (自 R2022b 起) |
socCreateModel | Creates a skeleton SoC Blockset for AMD model for task set (自 R2022b 起) |
对象
socModelBuilder | Build, load, and execute SoC model on SoC and FPGA boards (自 R2023a 起) |
主题
处理器、可编程逻辑和内存
- SoC Blockset Model Structure (SoC Blockset)
Top level structure of SoC model. - Use Template to Create SoC Model
Create SoC models using Simulink project templates.
- Create an SoC Project Application (SoC Blockset)
Step-by-step instructions and guidelines for creating an SoC project and models for an SoC application. - Use SoC Builder to Generate SoC Design (SoC Blockset)
Generate an SoC design and run it on an SoC device using the SoC Builder tool. - Export Custom Reference Design from SoC Model (SoC Blockset)
Use thesocExportReferenceDesignfunction to export a custom reference design from an SoC Blockset™ for AMD model. - Generate SoC Software Model (SoC Blockset)
Generate Simulink software models using the IP core generation workflow. - Custom Hardware Board Configuration (SoC Blockset)
Develop an SoC application model with a custom board configuration.
架构和分析
- Using the Algorithm Analyzer Report (SoC Blockset)
Navigate details of the report generated by thesocModelAnalyzerorsocFunctionAnalyzerfunction.
疑难解答
Build Error When FPGA or Processor Model Not Detected (SoC Blockset)
Unsupported mode in when generating SoC design using SoC Builder.
Build Error for Rapid Accelerator Mode (SoC Blockset)
Unsupported simulation mode in SoC Blockset for AMD models and projects.
精选示例
Streaming Data from Hardware to Software Using Altera SoC Devices
A systematic approach to design the data-path between hardware logic (FPGA) and embedded processor using SoC builder workflow.
Streaming Data from Software to Hardware Using Altera SoC Devices
Design the data-path from an embedded processor to hardware logic (FPGA) using SoC builder workflow. Design and simulate the entire application comprising of FPGA and processor algorithms, memory interface, and task scheduling to meet the system requirements. Then, validate the design on hardware by generating code from the model and implementing it on a System-on-Chip (SoC) device.
Triggering Software Tasks by FPGA Interrupts Using Altera SoC Devices
Model an algorithm partitioned between hardware and software. The hardware IP is implemented in FPGA fabric, and triggers a software task implemented in the embedded processor. Design, simulate, and implement a complete design on SoC hardware.
