速度与面积优化规范
针对目标设备部署的速度与面积优化设计的推荐规范
HDL 建模规范是一组推荐规范，用于创建 Simulink® 模型、MATLAB Function 模块和 Stateflow® 图以通过 HDL Coder™ 生成代码。除了提供架构指导外，因为生成的代码以 FPGA、ASIC 和 SoC 等硬件平台为目标，您可以使用这些规范针对目标硬件上的速度或面积来优化设计。
主题
规范列表与严重级别
- Guidelines for Speed and Area Optimizations - By Numbered List
List of speed and area optimization guidelines in ascending order of Guideline ID. - HDL Modeling Guidelines Severity Levels
Various severity levels associated with the HDL modeling guidelines and their description.
面积优化规范
- Resource Sharing Settings for Various Blocks
Recommended settings for using the resource sharing optimization effectively for various blocks. - Resource Sharing of Subsystems and Floating-Point IPs
Recommended settings for using the resource sharing optimization effectively for Subsystems and floating-point IPs. - Resource Sharing Guidelines for Vector Processing and Matrix Multiplication
Resource sharing is an area optimization in which HDL Coder identifies multiple functionally equivalent resources and replaces them with a single resource.
速度优化规范
- Distributed Pipelining and Clock-Rate Pipelining Guidelines
The code generator introduces registers when you specify certain block implementations or use certain settings. - Insert Distributed Pipeline Registers for Blocks with Vector Data Type Inputs
Recommended settings for using the distributed pipelining optimization effectively with vector inputs.
