性能、功率和面积优化
R2026b通过使用以下 HDL 优化来满足目标硬件的时序和面积需求：
面积优化可减少设计的资源使用量。
性能优化可改进设计在目标 FPGA 上的时序，使设计以更高频率运行。
I/O 优化可减少使用大型输入的算法的 I/O。
此外，HDL Coder 还提供有助于平衡速度、面积、吞吐量和延迟的优化。有关优化方法的详细信息，请参阅Introduction to Optimizations in HDL Coder和Enabling Optimizations in HDL Coder。
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精选示例
Use Multicycle Path Constraints to Meet Timing for Slow Paths
Apply multicycle path constraints in your design to meet timing requirements. Using multicycle path constraints can save area and reduce synthesis run times. For more information, see Enable-Based Multicycle Path Constraints.
Use Delay Absorption While Modeling with Latency
Model with latency to absorb design delays and prevent a timing mismatch between the original and generated model.
Generate IP Core for Frame-Based Model with AXI4 Stream Interfaces
Leverage the frame to sample optimization from HDL Coder™ to generate a sample-based IP core with AXI4-Stream interfaces from a frame-based Simulink® model. The generated IP core can then be deployed to hardware and verified using live streaming data from MATLAB®.
Distributed Pipelining: Speed Optimization
Optimize a Simulink® design for speed by using the distributed pipelining optimization.
