SystemVerilog DPI Test Bench

Generate DPI test bench code from entire Simulink model (requires HDL Verifier™)

When you generate HDL code from a subsystem, you can optionally generate a SystemVerilog test bench. This test bench verifies the generated HDL code by using a C component generated from the entire Simulink^® model.

You can access this feature in HDL Workflow Advisor under HDL Code Generation > Set Testbench Options, or in the Model Configuration Parameters dialog box, under HDL Code Generation > Test Bench. Or, for command-line access, set the GenerateSVDPITestBench property of makehdltb.

Functions

makehdltb Generate HDL test bench from model or subsystem

Topics

Verify HDL Design Using SystemVerilog DPI Test Bench
This example shows how to use SystemVerilog DPI test bench for verification of HDL code where a large data set is required.
Choose a Test Bench for Generated HDL Code
Select a generated test bench.