Get Started with IP Core Generation for Intel Quartus Pro Based Devices

Requirements

This example requires:

Set Up Intel SoC Hardware and Tools

1. Set up the Arria 10 SoC as shown in the figure below. To learn more about the Arria 10 SoC hardware setup, refer to the board documentation.

1.1 Set up the DIP switches and jumper settings as shown in the figure below.

1.2 Connect the USB UART using a Micro-USB cable to your computer. Ensure your USB device drivers, such as for the FTDI USB to UART, are installed correctly.

1.3 Connect the Arria10 SoC kit to your computer using an Ethernet cable.

2. Install the HDL Coder Support Package for Intel FPGA and SoC Devices and Embedded Coder Support Packages for Intel SoC Devices. To start the installer, open MATLAB and , in the Home tab click Add-Ons > Get Hardware Support Packages.

3. Ensure you are using the SD card image provided by the Embedded Coder Support Package for Intel SoC Devices. If you need to update your SD card image, refer to the Hardware Setup section of Add Support for Intel SoC Platform (Embedded Coder).

4. Set up the Arria10 SoC hardware connection by entering:

h = alterasoc

The alterasoc function logs in to the hardware via the COM port and runs the ifconfig command to obtain the IP address of the board. This function also tests the Ethernet connection.

5. You can optionally test the serial connection by using the following configuration and a program such as PuTTY™.

*Baud rate: 115200 *Data bits: 8 *Stop bits: 1 *Parity: None *Flow control: None. You should be able to observe Linux booting log on the serial console when you power cycle the Arria10 SoCKit board. You must close this serial connection before using the alterasoc function again.

6. Set up the Intel Quartus Pro synthesis tool path by entering this command. Use your own Quartus installation path when you run the command.

hdlsetuptoolpath('ToolName', 'Intel Quartus Pro', 'ToolPath', 'C:\intelFPGA\23.3\quartus\bin64\qpro.exe');

If you are using an Intel QUARTUS II, use the follow command:

hdlsetuptoolpath('ToolName', 'Intel QUARTUS II', 'ToolPath', 'C:\intelFPGA\22.1.1\quartus\bin64\quartus.exe');

Partition your design for hardware and software implementation

The first step of the Intel SoC hardware-software co-design workflow is to decide which parts of your design to implement on the programmable logic, and which parts to run on the ARM processor.

Group all the blocks you want to implement on programmable logic into an atomic subsystem. This atomic subsystem is the boundary of your hardware-software partition. All the blocks inside this subsystem are implemented on programmable logic, and all the blocks outside this subsystem will run on the ARM processor.

In this example, the subsystem led_counter is the hardware subsystem. It models a counter that blinks the LEDs on an FPGA board. Two input ports, Blink_frequency and Blink_direction, are control ports that determine the LED blink frequency and direction. All the blocks outside of the subsystem led_counter are for software implementation.

In Simulink, you can use the Slider Gain or Manual Switch block to adjust the input values of the hardware subsystem. In the embedded software, this means the ARM processor controls the generated IP core by writing to the AXI interface accessible registers. The output port of the hardware subsystem, LED, connects to the LED hardware. The output port, Read_Back, can be used to read data back to the processor.

open_system('hdlcoder_led_blinking_4bit');

Generate an HDL IP core using the HDL Workflow Advisor

Using the IP Core Generation workflow in the HDL Workflow Advisor enables you to automatically generate a sharable and reusable IP core module from a Simulink model. The generated IP core is designed to be connected to an embedded processor on an FPGA device. HDL Coder generates HDL code from the Simulink blocks, and also generates HDL code for the AXI interface logic connecting the IP core to the embedded processor. HDL Coder packages all the generated files into an IP core folder. You can then integrate the generated IP core with a larger FPGA embedded design in the Intel Qsys environment.

1. Start the IP core generation workflow.

1.1. Open the HDL Workflow Advisor from the hdlcoder_led_blinking_4bit/led_counter subsystem by right-clicking the led_counter subsystem, and choosing HDL Code > HDL Workflow Advisor.

1.2. In the Set Target > Set Target Device and Synthesis Tool task, for Target workflow, select IP Core Generation.

1.3. For Target platform, select Intel Arria 10 SoC development kit. If you don't have this option, select Get more to open the Support Package Installer. In the Support Package Installer, select Intel FPGA and SoC Devices and follow the instructions provided by the Support Package Installer to complete the installation.

1.4. Select the Synthesis tool as Intel Quartus Pro (or Altera QUARTUS II)

1.5. Click Run This Task to run the Set Target Device and Synthesis Tool task.

1.6. In the Set Target > Set Target Reference Design task, choose Default system. For this example, it is selected by default.

1.7. Click Run This Task to run the Set Target Reference Design task.

2. Configure the target interface.

Map each port in your DUT to one of the IP core target interfaces. In this example, input ports Blink_frequency and Blink_direction are mapped to the AXI4 interface, so HDL Coder generates AXI interface accessible registers for them. The LED output port is mapped to an external interface, LEDs General Purpose [0:3], which connects to the LED hardware on the Intel SoC board.

2.1 In the Set Target > Set Target Interface task, choose AXI4 for Blink_frequency, Blink_direction, and Read_back.

2.2 Choose LEDs General Purpose [0:3] for LED.

2.3 In the Set Target > Set Target Frequency task, choose Target Frequency as 50 MHz.

3. Generate the IP Core.

To generate the IP core, right-click the Generate RTL Code and IP Core task and select Run to Selected Task.

4. Generate and view the IP core report.

After you generate the custom IP core, the IP core files are in the ipcore folder within your project folder. An HTML custom IP core report is generated together with the custom IP core. The report describes the behavior and contents of the generated custom IP core.

5. Follow step 1 of Integrate the IP core with the Intel Qsys environment section of Get Started with IP Core Generation for Intel SoC Devices example to integrate the IP core in the reference design and create the Qsys project.

6. Now let us examine the Intel Qsys project created by the SoC workflow after completing the Create Project task under Embedded System Integration. The following figure shows the SoC project where we have highlighted the HDL IP Core. It is instructive to compare this project with the previous project used in the custom reference design plugin for a deeper understanding of the relationship between a custom reference design and an HDL IP Core.

7. Follow the steps 2, 3 and 4 of Integrate the IP core with the Intel Qsys environment section of Get Started with IP Core Generation for Intel SoC Devices example to generate software interface model, generate FPGA bitstream and program target device respectively.

8. The LEDs on the Arria 10 SoC will start blinking after loading the bitstream. In addition, you can control the LED blink frequency and direction by executing the software interface model. Refer to the example Get Started with IP Core Generation for Intel SoC Devices example to control the LED blink frequency and direction from the generated software interface model.

If you want to create a reference design, see Create a reference design using Intel Quartus Pro. To register the custom reference design, see Register the custom reference design in the HDL Workflow Advisor.

Create a Reference Design Using Intel Quartus Pro

A reference design captures the complete structure of an SoC design and defines the different components and their interconnections. HDL Coder generates an IP core that integrates with the reference design, and is then used to program an SoC board. The following figure describes the relationship between a reference design, an HDL IP core, and an SoC board.

Follow these steps to create and export a simple reference design using the Intel Quartus Pro and Platform Designer (Qsys) environment. For more information about the QSys system integration tool, refer to Intel documentation.

1. Create an empty Quartus project using the New Project wizard. Enter the device part number as shown in this figure:

2. Initialize the Platform Designer(Qsys) in Quartus Pro by navigating to Tools --> Platform Designer as shown in the following figure.

3. Select Hard Processor System Intel Arria 10 FPGA IP(HPS), clock and reset IPs from IP catalog to the created Platform Designer project. Connect the required clocks and resets to the Arria 10 HPS IP as shown in the following figure. complete the other settings required for Arria 10 Hard Processor System such as Peripheral pin set and mode settings.

4. Keep h2f_axi_master port connection open in order to connect to DUT IP during the process of workflow IP integration. Complete the rest of the connections between Altera PLL IP and HPS IP as shown in the following figure.

5. Save the Qsys file. This file is used when you create reference design plugin.

Register the Intel Arria 10 SoC development kit

In this section, You register the Intel Arria 10 SoC development kit in HDL Workflow Advisor.

1. Create a board registration file with the name hdlcoder_board_customization.m and add it to the MATLAB path.

For more details on creating a board registration file, refer to Define Custom Board and Reference Design for Intel Workflow.

2. Create the board definition file.

A board definition file contains information about the SoC board.

For more details on creating the board definition file, refer to Define Custom Board and Reference Design for Intel Workflow.

Register the custom reference design in HDL Workflow Advisor

In this section, You register the custom reference design in HDL Workflow Advisor.

1. Create a reference design registration file named hdlcoder_ref_design_customization.m containing a list of reference design plugins associated with an SoC board.

For more details on creating a custom reference design, refer to Define Custom Board and Reference Design for Intel Workflow.

2. Create the reference design definition file.

A reference design definition file defines the interfaces between the custom reference design and the HDL IP core that is generated by the HDL Coder SoC workflow. For more details on creating the reference design definition file, refer to Define Custom Board and Reference Design for Intel Workflow.

Early I/O for Arria 10: The Intel Arria 10 SoC FPGA device supports Early I/O Release.

Early IO release allows you to enable DDR functioning prior programming the core raw binary file (RBF) for speeding up the boot time. In this flow, the shared I/O and hard memory controller I/O are configured and released allowing HPS immediate access to them.

This feature splits the FPGA configuration sequence into two parts. The first part configures the FPGA I/O, the Shared I/O and also enables the HPS External Memory Interface (EMIF) if present. The second part of the sequence configures the core FPGA fabric. By splitting the configuration sequence, the Arria10 Hard Processing System now has access to Shared I/O and EMIF before the FPGA fabric is configured. This allows more flexibility for designs that need faster boot times or alternate boot sources. In this Early I/O, two Raw Binary Format (.rbf) files are generated: (1) peripheral.rbf file. (2) core.rbf file. Together, these configuration files contain the same data as a combined configuration .rbf file that is generated when the Early I/O Release feature is not used. The peripheral.rbf file is loaded first and configures the FPGA I/O, Shared I/O and HPS EMIF. The core.rbf is loaded next and completes the FPGA configuration sequence by configuring the FPGA fabric. After the peripheral.rbf is successfully loaded, the Intel Arria 10 SoC FPGA HPS EMIF pins are released and the interface begins calibration.

To use this feature, you need to enable a reference design parameter hRD.GenerateSplitBitstream = true; as shown in the below plugin_rd file. Accordingly if this reference design parameter is made true, it generates two .rbf files for configuring the FPGA as mentioned above.

The contents of this reference design definition file plugin_rd.m is similar to the Intel Quartus standard version, the differences for the Intel Quartus Pro are listed below.

function hRD = plugin_rd()
% Reference design definition

% Construct reference design object
hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Intel Quartus Pro');

%% Add custom design files
% add custom Qsys design
hRD.addCustomQsysDesign( ...
    'CustomQsysPrjFile', 'system_soc.qsys');

% split the full rbf file into core and peripheral rbf files for Early I/O feature
hRD.GenerateSplitBitstream = true;