Model Design and Compatibility Guidelines

Model Design and Compatibility Guidelines - By Numbered List

The HDL modeling guidelines are a set of recommended guidelines that you can follow when creating Simulink^® model for code generation with HDL Coder™. The model design and compatibility guidelines consist of guidelines for basic block usage, clock and reset signals, buses and vectors, and subsystem and hierarchical designing. Each modeling guideline for HDL code generation has a different level of severity that indicates the levels of compliance requirements. To learn more about these severity levels, see HDL Modeling Guidelines Severity Levels.

These tables list the model design and compatibility guidelines in HDL Coder. These guidelines start from 1.1 and are divided into subsections. In the table, you see that certain guidelines have an associated model check. You can follow the modeling pattern recommended for these guidelines by running that check in the HDL Code Advisor. To learn more about the HDL Code Advisor, see Check HDL Compatibility of Simulink Model Using HDL Code Advisor.

Guidelines 1.1: Basic Settings

Guideline ID	Title	Severity	Associated Model Check/Coding Standard Rule
1.1.1	Use HDL-Supported Blocks	Recommended	None
1.1.2	Partition Model into DUT and Test Bench	Recommended	None
1.1.3	Avoid Using Double-Byte Characters	Mandatory	None
1.1.4	Document Model Features and Attributes	Recommended	None
1.1.5	Customize hdlsetup Function Based on Target Application	Recommended	Model Check: Check for model parameters suited for HDL code generation
1.1.6	Check Subsystem for HDL Compatibility	Recommended	None
1.1.7	Run Model Checks for HDL Coder	Recommended	None
1.1.8	Modeling with Simulink, Stateflow, and MATLAB Function Blocks	Informative	None
1.1.9	Terminate Unconnected Block Outputs	Mandatory	None
1.1.10	Using Comment Out and Comment Through of Blocks	Informative	None
1.1.11	Adjust Sizes of Constant and Gain Blocks for Identifying Parameters	Recommended	None
1.1.12	Display Parameters That Affect HDL Code Generation	Recommended	None
1.1.13	Change Block Parameters by Using find_system and set_param	Informative	None

Guidelines 1.2: DUT Subsystem and Hierarchical Modeling

Guideline ID	Title	Severity	Associated Model Check/Coding Standard Rule
1.2.1	DUT Subsystem Considerations	Strongly Recommended	Model Check: Check for invalid top level subsystem
1.2.2	Convert DUT Subsystem to Model Reference for Testbenches with Continuous Blocks	Strongly Recommended	None
1.2.3	Insert Handwritten Code into Simulink Modeling Environment	Informative	None
1.2.4	Avoid Constant Block Connections to Subsystem Port Boundaries	Mandatory	None
1.2.5	Generate Parameterized HDL Code for Constant and Gain Blocks	Recommended	None
1.2.6	Place Physical Signal Lines Inside a Subsystem	Mandatory	None

Guidelines 1.3: Vectors, Matrices, and Buses

Guideline ID	Title	Severity	Associated Model Check/Coding Standard Rule
1.3.1	Modeling Requirements for Matrices	Mandatory	None
1.3.2	Avoid Generating Ascending Bit Order in HDL Code From Vector Signals	Strongly Recommended	None
1.3.3	Use Buses to Improve Readability of Model and Generate HDL Code	Informative	None

Guidelines 1.4: Clock Bundle Signals

Guideline ID	Title	Severity	Associated Model Check/Coding Standard Rule
1.4.1	Use Global Oversampling to Create Frequency-Divided Clock	Informative	None
1.4.2	Create Multirate Model with Integer Clock Multiples by Clock Division	Mandatory	None
1.4.3	Use Dual Rate Dual Port RAM for Noninteger Multiple Sample Times	Mandatory	None
1.4.4	Asynchronous Clock Modeling in HDL Coder	Recommended	None
1.4.5	Use Global Reset Type Setting Based on Target Hardware	Strongly Recommended	Model check: Check for global reset setting for Xilinx and Altera devices

Guidelines 1.5: Native Floating Point

Guideline ID	Title	Severity	Associated Model Check/Coding Standard Rule
1.5.1	Modeling with Native Floating Point	Recommended	None