检测并消除 Bug

Use input port minimum and maximum values as analysis constraints by Simulink® Design Verifier™ during both test generation and property proving.

Detect integer overflow errors in a model by using design error detection analysis. Simulink® Design Verifier™ identifies the model constructs that may result in integer overflows and then either proves that the integer overflow cannot occur during simulation or generates test cases that demonstrates the integer overflow error.

Detect out of bound array access errors in a model.

Demonstrates how to isolate potential causes of dead logic using the sldvexCommonCausesOfDeadLogic model. Dead logic detection finds unreachable objectives in the model that cause the model element to remain inactive.