SoC Blockset

Design, analyze, and deploy hardware/software applications for AMD and Intel SoC devices

SoC Blockset enables you to simulate and analyze the performance of algorithms on programmable SoCs and ASICs. You can deploy these algorithms as hardware and software applications for prototyping and production.

The blockset lets you build Simulink models of hardware architectures by defining interfaces between Arm^® processor cores, hardware logic, memory, and peripherals. You can use models to partition algorithms between hardware logic and processors to analyze implementation tradeoffs.

The SoC Builder app automates deployment by building IP cores and software, then programming development boards (with HDL Coder and Embedded Coder).

SoC Blockset analyzes applications in hardware with performance diagnostics and software profiling. Supported devices include AMD^® Versal™ Adaptive SoCs, Zynq™ UltraScale+™ MPSoCs/RFSoCs, and Zynq-7000 SoCs, as well as Intel^® SoC FPGAs.

Modeling and Simulation | Designing a Datapath from an FPGA to a Processor with SoC Blockset

Block diagram of 5G NR SIB1 recovery for FR1 and FR2.

5G and SDR Applications

With Wireless HDL Toolbox, simulate and deploy a 5G NR MIB recovery algorithm or a 5G NR SIB1 recovery algorithm for FR1 and FR2 using an SoC Blockset implementation. Use Zynq-based radios with Analog Devices RF cards to prototype, verify, and test practical wireless systems.

Documentation | Examples

Simulink model of lane detection algorithm with an AMD ZC706 board.

Vision Applications

Build models using SoC reference designs that enable capturing live video to simulation, processing video streams on hardware, and integration with deep learning processors. Develop prototype designs with live video input using the SoC Blockset hardware support package.

Documentation | Examples

Block diagram and SoC Blockset model for a field-oriented control algorithm.

Motor and Power Electronics Controls Applications

Model and simulate motor and power electronics controllers partitioned between processors and programmable logic. Automate C code generation and compilation along with IP core generation to target AMD Zynq and Versal devices as well as Intel SoC FPGAs.

Documentation | Example

Versal AI Core series VCK190 evaluation kit hardware.

Target Versal Devices

Analyze system designs using predefined models of the latest AMD programmable SoC devices, then use the SoC Builder tool to deploy to development boards for testing.

Documentation | Example

Target RFSoC Devices

Simulate and deploy radar applications targeted to AMD RFSoC devices. Deploy 5G signal detection algorithms to RFSoC boards, using SoC Blockset to program the hardware, load test data into memory, and control the deployed design. Implement frequency-hopping algorithms for CDMA and FHSS applications with AMD UltraScale+ RFSoCs.

Documentation | Examples (Wireless communications, Radar)

Clockwise from left: ZC706, ZedBoard, Arty, ZC702 and PicoZed.

Target AMD UltraScale+ MPSoC and Zynq-7000 Devices

Develop applications such as motor/power electronics controls or wireless communications for implementation on MPSoC and Zynq-7000 platforms. Use the SoC Builder app to configure, build, and deploy hardware/software algorithms to prototype hardware.

Documentation | Example

Screenshot of the Hardware Setup app for Xilinx boards.

COTS Boards and Custom Board Support

Use the OS Customizer tool to modify and add libraries to the Linux^® distribution for your embedded processor. Customize the embedded Linux operating system of supported boards.

Documentation | Examples

Model DDR Memory

Model DDR memory and simulate shared memory transactions between hardware logic and embedded processors. Configure DMA controllers to arbitrate memory traffic. Account for memory latency and throughput in simulation.

Documentation | Examples

Contents of reference designs, including RAMs, memory controllers, data/control interfaces, FIFOs, clock managers, and control paths.

Generate HDL Coder Reference Designs

Generate HDL Coder reference designs directly from SoC Blockset models, then use the HDL Workflow Advisor tool to integrate IP cores created with HDL Coder.

Documentation | Examples