时钟与多速率设计

R2026b

为具有单时钟或多时钟的多速率模型生成 HDL 代码

为具有单个或多个时钟及时钟控制元素（如时钟复位和时序控制器）的多速率模型生成 HDL 代码。

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Generate a Global Oversampling Clock
Generate a global oversampling clock to integrate your DUT into a larger design.
Specify the Clock Enable Rate
Configure clock enable to run at design base rate or input data rate.
Minimize Clock Enables
Generate code for registers without clock enables.
Generate Clock Enable Signals
Generation of clock enable signals in your DUT for single rate and multirate models.
Generate Reset for Timing Controller
How to generate reset for timing controller.
Use Triggered Subsystem in HDL Code Generation
Best practices for using Triggered Subsystems, Trigger As Clock setting in HDL code generation.
Generation of Clock Bundle Signals in HDL Coder
How HDL Coder™ generates clock, reset, and clock enable signals in the HDL code.
Customize Clock Bundle Names in Generated Code
Learn how to customize clock bundle names in the generated code.

Code Generation from Multirate Models
Overview of HDL code generation for single-clock, single-tasking multirate models.
Multirate Model Requirements for HDL Code Generation
Guidelines for setting up multirate models and blocks for HDL code generation.
Timing Controller for Multirate Models
Learn about timing controllers and clock enables in a multirate model.
Use Triggered Subsystem for Asynchronous Clock Domain
Design a model for an asynchronous clock domains using triggered subsystems.