时钟与多速率设计

多速率模型的时钟生成和 HDL 代码生成规范

为具有单个或多个时钟及时钟控制元素（如时钟复位和时序控制器）的多速率模型生成 HDL 代码。

主题

Generate a Global Oversampling Clock
Generate a global oversampling clock to integrate your DUT into a larger design.
Code Generation from Multirate Models
Overview of HDL code generation for single-clock, single-tasking multirate models.
Multirate Model Requirements for HDL Code Generation
Guidelines for setting up multirate models and blocks for HDL code generation.
Timing Controller for Multirate Models
Learn about timing controllers and clock enables in a multirate model.
Generate Reset for Timing Controller
How to generate reset for timing controller.
Using Triggered Subsystems for HDL Code Generation
How to use Triggered Subsystems, Trigger As Clock property, and generate HDL code.
Use Triggered Subsystem for Asynchronous Clock Domain
Design a model for an asynchronous clock domains using triggered subsystems.
Generate Clock Enable Signals
Generation of clock enable signals in your DUT for single rate and multirate models.

Instantiate multiple top-level synchronous clock input ports in HDL Coder™.

Learn various example designs that use multiple sample rates with IP Core Generation workflow.

You can generate HDL code for a system with multiple independent clock domains using HDL Coder™ by: