6-Phase Inverse VSD Transform

Compute vector space decomposition (VSD) based inverse transformation on orthogonal inputs

Since R2024b

Libraries:
Motor Control Blockset / Controls / Math Transforms
Motor Control Blockset HDL Support / Controls / Math Transforms

Description

The 6-Phase Inverse VSD Transform block applies inverse vector space decomposition (VSD) transform on the orthogonal inputs (α, β, x, y, z₊, and z_-) to compute the six-phase outputs (a1, b1, c1, a2, b2, and c2).

The six orthogonal input components belong to the following three subspaces:

α-β subspace (containing α and β components)
x-y subspace (containing x and y components)
Zero sequence subspace (containing z₊ and z_- components)

The block outputs the six signals as two sets of three-phase signals.

You can use the block to determine the six-phase stator voltages or currents of an asymmetric or a symmetric six-phase permanent magnet synchronous motor (PMSM) using the six orthogonal input components. For example, you can use this block to determine the reference six-phase stator voltages from the α, β, x, and y reference voltage components generated by the current PI controllers. Therefore, you can use this block to implement field-oriented control (FOC) of an asymmetric six-phase PMSM. For more information, see Field-Oriented Control of Six-Phase PMSM.

Six-phase motors have different configurations based on the spatial angle (or spatial shift) between the two sets of three-phase windings. An asymmetric six-phase PMSM uses a spatial angle of 30 electrical degrees, whereas a symmetric six-phase PMSM uses a spatial angle of 60 electrical degrees.

The following image shows the comparison between input signals α and β as well as the output signals a₁ and b₁.

For more information about the block algorithm, see Algorithm.

Examples

Field-Oriented Control of Six-Phase PMSM

Control the torque of an asymmetric six-phase permanent magnet synchronous motor (PMSM) using field-oriented control (FOC).

Open Model

Ports

Input

expand all

αβxyz₊z_- — Six axis orthogonal components in three different subspaces
scalar

Six axis orthogonal input components (α, β, x, y, z₊, and z_-) in the following three subspaces:

α-β subspace (containing α and β components)
x-y subspace (containing x and y components)
Zero sequence subspace (containing z₊ and z_- components)

Data Types: single | double | fixed point

Output

expand all

a₁b₁c₁ — First set of three-phase outputs
scalar

First set of three-phase outputs, such that phase a1 axis aligns with the α axis. For a six-phase PMSM, this port outputs the three-phase stator voltages or currents belonging to the first three-phase winding set.

Data Types: single | double | fixed point

a₂b₂c₂ — Second set of three-phase outputs
scalar

Second set of three-phase outputs. For a six-phase PMSM, this port outputs the three-phase stator voltages or currents belonging to the second three-phase winding set.

Data Types: single | double | fixed point

Parameters

expand all

Power invariant — Option to enable power invariant transformation
`off` (default) | on

Select this parameter to enable the block to use power invariant transformation. If you clear this parameter, the block uses amplitude invariant transformation.

Motor type — Type of six-phase PMSM
`Asymmetric (30 degree offset)` (default) | `Symmetric (60 degree offset)`

Select the type of six-phase PMSM for which you want to compute the inverse VSD transformation.

Algorithms

The following equations describe the inverse VSD transformation on the six orthogonal input components for an asymmetric PMSM.

$[\begin{array}{l} a 1 \\ b 1 \\ c 1 \\ a 2 \\ b 2 \\ c 2 \end{array}] = (σ) [\begin{matrix} 1 & 0 & 1 & 0 & 1 & 0 \\ \frac{- 1}{2} & \frac{\sqrt{3}}{2} & \frac{- 1}{2} & \frac{- \sqrt{3}}{2} & 1 & 0 \\ \frac{- 1}{2} & \frac{- \sqrt{3}}{2} & \frac{- 1}{2} & \frac{\sqrt{3}}{2} & 1 & 0 \\ \frac{\sqrt{3}}{2} & \frac{1}{2} & \frac{- \sqrt{3}}{2} & \frac{1}{2} & 0 & 1 \\ \frac{- \sqrt{3}}{2} & \frac{1}{2} & \frac{\sqrt{3}}{2} & \frac{1}{2} & 0 & 1 \\ 0 & - 1 & 0 & - 1 & 0 & 1 \end{matrix}] \times [\begin{array}{l} α \\ β \\ x \\ y \\ z_{+} \\ z_{-} \end{array}]$

where,

$\begin{array}{l} σ = 1 (for amplitude invariant transformation) \\ = \frac{1}{\sqrt{3}} (for power invariant transformation) \end{array}$

The following equations describe the inverse VSD transformation on the six orthogonal input components for an symmetric PMSM.

$[\begin{array}{l} a 1 \\ b 1 \\ c 1 \\ a 2 \\ b 2 \\ c 2 \end{array}] = (σ) [\begin{matrix} 1 & 0 & 1 & 0 & 1 & 0 \\ \frac{- 1}{2} & \frac{\sqrt{3}}{2} & \frac{- 1}{2} & \frac{- \sqrt{3}}{2} & 1 & 0 \\ \frac{- 1}{2} & \frac{- \sqrt{3}}{2} & \frac{- 1}{2} & \frac{\sqrt{3}}{2} & 1 & 0 \\ \frac{1}{2} & \frac{\sqrt{3}}{2} & \frac{- 1}{2} & \frac{\sqrt{3}}{2} & 0 & 1 \\ - 1 & 0 & 1 & 0 & 0 & 1 \\ \frac{1}{2} & \frac{- \sqrt{3}}{2} & \frac{- 1}{2} & \frac{- \sqrt{3}}{2} & 0 & 1 \end{matrix}] \times [\begin{array}{l} α \\ β \\ x \\ y \\ z_{+} \\ z_{-} \end{array}]$

where,

$\begin{array}{l} σ = 1 (for amplitude invariant transformation) \\ = \frac{1}{\sqrt{3}} (for power invariant transformation) \end{array}$

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties


ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).
SharingFactor	Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing (HDL Coder).

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced in R2024b

6-Phase Inverse VSD Transform

Description

Examples

Field-Oriented Control of Six-Phase PMSM

Ports

Input

αβxyz₊z_- — Six axis orthogonal components in three different subspaces
scalar

Output

a₁b₁c₁ — First set of three-phase outputs
scalar

a₂b₂c₂ — Second set of three-phase outputs
scalar

Parameters

Power invariant — Option to enable power invariant transformation
`off` (default) | on

Motor type — Type of six-phase PMSM
`Asymmetric (30 degree offset)` (default) | `Symmetric (60 degree offset)`

Algorithms

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Topics

6-Phase Inverse VSD Transform

Description

Examples

Field-Oriented Control of Six-Phase PMSM

Ports

Input

αβxyz+z- — Six axis orthogonal components in three different subspaces scalar

Output

a1b1c1 — First set of three-phase outputs scalar

a2b2c2 — Second set of three-phase outputs scalar

Parameters

Power invariant — Option to enable power invariant transformation off (default) | on

Motor type — Type of six-phase PMSM Asymmetric (30 degree offset) (default) | Symmetric (60 degree offset)

Algorithms

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Topics

αβxyz₊z_- — Six axis orthogonal components in three different subspaces
scalar

a₁b₁c₁ — First set of three-phase outputs
scalar

a₂b₂c₂ — Second set of three-phase outputs
scalar

Power invariant — Option to enable power invariant transformation
`off` (default) | on

Motor type — Type of six-phase PMSM
`Asymmetric (30 degree offset)` (default) | `Symmetric (60 degree offset)`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.