自定义 IP 核生成
HDL Coder™ 可以生成可部署到设备上的自定义 HDL IP 核。您可以将生成的 IP 核集成到默认系统参考设计中，或集成到为板注册的自定义参考设计中。
主题
- Generate an IP Core for AMD SoC Devices from MATLAB
IP core generation for AMD® SoC Devices from MATLAB®.
- Generate an IP Core for AMD SoC Devices from Simulink
IP core generation for AMD SoC Devices from Simulink®.
- IP Core Generation Workflow for AMD FPGA Boards
Learn how to use the IP Core Generation workflow with standalone FPGA devices and embed the IP core into the reference design.
- Custom IP Core Generation
Generate a custom IP core from a model or algorithm using the HDL Workflow Advisor.
- Custom IP Core Report
You generate an HTML custom IP core report by default when you generate a custom IP core.
- IP Caching for Faster Reference Design Synthesis
Use IP caching to speed up reference design synthesis time by using an out-of-context workflow.
疑难解答
Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows
Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.
精选示例
IP Core Generation Workflow with a MicroBlaze Processor
Use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Xilinx® parts without an embedded ARM® processor present, but which still utilize the HDL Coder generated AXI interface to control the DUT. Specifically, this example will use the Xilinx Kintex-7 KC705 board and a MicroBlaze™ soft processor running a LightWeightIP (lwIP) based TCP/IP firmware server in the reference design to access the HDL Coder generated DUT registers from anywhere on the connected network. Further, this example will also highlight the difference between accessing data from a collection of registers implemented as multiple scalar ports and a collection of registers implemented as a single vector port.
Prototype IP Core on RFSoC with FPGA I/O
Implement a quadrature phase shift keying (QPSK) wireless communication algorithm on the AMD® Zynq® UltraScale+™ ZCU216 evaluation kit or the Xilinx Zynq UltraScale+ ZCU111 evaluation kit. You generate HDL code for your algorithm, build and deploy the HDL design on an RFSoC device, and run a MATLAB® script to interactively capture data from the deployed HDL design.
