Custom IP Core Generation

Generate HDL IP core from your DUT for deployment to the default system reference design or custom reference design registered with the board

HDL Coder™ can generate a custom HDL IP core that you can deploy to the devices. You can integrate the generated IP core into the default system reference design or into your own custom reference design that you register for the board.

Topics

Generate an IP Core for Xilinx SoC Devices from MATLAB
IP core generation for Xilinx^® SoC Devices from MATLAB^®.
Generate an IP Core for Xilinx SoC Devices from Simulink
IP core generation for Xilinx SoC Devices from Simulink^®.
IP Core Generation Workflow for Xilinx FPGA Boards
Learn how to use the IP Core Generation workflow with standalone FPGA devices and embed the IP core into the reference design.
Custom IP Core Generation
Generate a custom IP core from a model or algorithm using the HDL Workflow Advisor.
Custom IP Core Report
You generate an HTML custom IP core report by default when you generate a custom IP core.
IP Caching for Faster Reference Design Synthesis
Use IP caching to speed up reference design synthesis time by using an out-of-context workflow.

Troubleshooting

Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.

Featured Examples

IP Core Generation Workflow with a MicroBlaze Processor

Use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Xilinx® parts without an embedded ARM® processor present, but which still utilize the HDL Coder generated AXI interface to control the DUT. Specifically, this example will use the Xilinx Kintex-7 KC705 board and a MicroBlaze™ soft processor running a LightWeightIP (lwIP) based TCP/IP firmware server in the reference design to access the HDL Coder generated DUT registers from anywhere on the connected network. Further, this example will also highlight the difference between accessing data from a collection of registers implemented as multiple scalar ports and a collection of registers implemented as a single vector port.

Open Script