参考设计集成和部署
您可以将生成的 IP 核集成到默认系统参考设计中,或集成到为板注册的自定义参考设计中。HDL Coder™ 可以生成 IP 核,将其集成到 Vivado® 工程中,并对硬件进行编程。使用 Embedded Coder®,您可以生成和编译嵌入式软件,并在 ARM® 处理器上运行它。
主题
- Default System Reference Design for AMD SoC Device
Learn about the default system reference design for AMD® SoC device and using the reference design.
- Default System Reference Design for AMD FPGA Board
Learn about the default system reference design for AMD FPGA board and using the reference design.
- Default System with AXI4-Stream Interface Reference Design
Learn about how to use the default system with AXI4-Stream Interface reference design and its requirements.
- Default Video System Reference Design
Learn about the default video system reference design and its requirements.
- Default System with External DDR Memory Access Reference Design
Learn about the default system with external DDR3, DDR4, and LPDDR4 memory access reference design and its requirements.
- Program Target FPGA Boards or SoC Devices
How to program the target Intel or Xilinx Hardware.