6-Phase VSD Transform

Compute vector space decomposition (VSD) based transformation on six-phase inputs

Since R2024b

Libraries:
Motor Control Blockset / Controls / Math Transforms
Motor Control Blockset HDL Support / Controls / Math Transforms

Description

The 6-Phase VSD Transform block applies vector space decomposition (VSD) transform (or decoupling transform) on six-phase inputs (a1, b1, c1, a2, b2, and c2) to generate the corresponding six axis components (α, β, x, y, z₊, and z_-) in the following three subspaces.

α-β subspace (containing α and β components)
x-y subspace (containing x and y components)
Zero sequence subspace (containing z₊ and z_- components)

The block accepts the six-phase inputs as two sets of three-phase signals.

You can use the block to determine these six axis components corresponding to the six-phase stator voltages or currents of an asymmetric or a symmetric six-phase permanent magnet synchronous motor (PMSM). For example, you can use this block to determine the α, β, x, and y components of the six-phase stator feedback currents and use them to implement field-oriented control (FOC) of an asymmetric six-phase PMSM. For more information, see Field-Oriented Control of Six-Phase PMSM.

Six-phase motors have different configurations based on the spatial angle (or spatial shift) between the two sets of three-phase windings. An asymmetric six-phase PMSM uses a spatial angle of 30 electrical degrees, whereas a symmetric six-phase PMSM uses a spatial angle of 60 electrical degrees.

By default, the block uses amplitude invariant transformation. However, you can use the parameter Power invariant to configure the block to use power invariant transformation.

The following image shows the comparison between input signals a₁ and b₁ as well as the output signals α and β.

For more information about the block algorithm, see Algorithm.

Examples

Field-Oriented Control of Six-Phase PMSM

Control the torque of an asymmetric six-phase permanent magnet synchronous motor (PMSM) using field-oriented control (FOC).

Open Model

Ports

Input

expand all

a₁b₁c₁ — First set of three-phase inputs
scalar

First set of three-phase inputs. For a six-phase PMSM, this port accepts the three-phase stator voltages or currents belonging to the first three-phase winding set.

Data Types: single | double | fixed point

a₂b₂c₂ — Second set of three-phase inputs
scalar

Second set of three-phase inputs. For a six-phase PMSM, this port accepts the three-phase stator voltages or currents belonging to the second three-phase winding set.

Data Types: single | double | fixed point

Output

expand all

αβxyz₊z_- — Six axis components in three different subspaces
scalar

Six axis components (α, β, x, y, z₊, and z_-) in the following three subspaces, such that phase a1 axis aligns with the α axis:

α-β subspace (containing α and β components)
x-y subspace (containing x and y components)
Zero sequence subspace (containing z₊ and z_- components)

Data Types: single | double | fixed point

Parameters

expand all

Power invariant — Option to enable power invariant transformation
`off` (default) | on

Select this parameter to enable the block to use power invariant transformation. If you clear this parameter, the block uses amplitude invariant transformation.

Motor type — Type of six-phase PMSM
`Asymmetric (30 degree offset)` (default) | `Symmetric (60 degree offset)`

Select the type of six-phase PMSM for which you want to compute the VSD transformation.

Algorithms

The following equations describe the VSD based transformation on the six-phase inputs for an asymmetric PMSM.

$[\begin{array}{l} α \\ β \\ x \\ y \\ z_{+} \\ z_{-} \end{array}] = σ \times [\begin{matrix} 1 & \frac{- 1}{2} & \frac{- 1}{2} & \frac{\sqrt{3}}{2} & \frac{- \sqrt{3}}{2} & 0 \\ 0 & \frac{\sqrt{3}}{2} & \frac{- \sqrt{3}}{2} & \frac{1}{2} & \frac{1}{2} & - 1 \\ 1 & \frac{- 1}{2} & \frac{- 1}{2} & \frac{- \sqrt{3}}{2} & \frac{\sqrt{3}}{2} & 0 \\ 0 & \frac{- \sqrt{3}}{2} & \frac{\sqrt{3}}{2} & \frac{1}{2} & \frac{1}{2} & - 1 \\ 1 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 1 \end{matrix}] \times [\begin{array}{l} a 1 \\ b 1 \\ c 1 \\ a 2 \\ b 2 \\ c 2 \end{array}]$

where,

$\begin{array}{l} σ = \frac{1}{3} (for amplitude invariant transformation) \\ = \frac{1}{\sqrt{3}} (for power invariant transformation) \end{array}$

The following equations describe the VSD based transformation on the six-phase inputs for a symmetric PMSM.

$[\begin{array}{l} α \\ β \\ x \\ y \\ z_{+} \\ z_{-} \end{array}] = (σ) [\begin{matrix} 1 & \frac{- 1}{2} & \frac{- 1}{2} & \frac{1}{2} & - 1 & \frac{1}{2} \\ 0 & \frac{\sqrt{3}}{2} & \frac{- \sqrt{3}}{2} & \frac{\sqrt{3}}{2} & 0 & \frac{- \sqrt{3}}{2} \\ 1 & \frac{- 1}{2} & \frac{- 1}{2} & \frac{- 1}{2} & 1 & \frac{- 1}{2} \\ 0 & \frac{- \sqrt{3}}{2} & \frac{\sqrt{3}}{2} & \frac{\sqrt{3}}{2} & 0 & \frac{- \sqrt{3}}{2} \\ 1 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 1 \end{matrix}] \times [\begin{array}{l} a 1 \\ b 1 \\ c 1 \\ a 2 \\ b 2 \\ c 2 \end{array}]$

where,

$\begin{array}{l} σ = \frac{1}{3} (for amplitude invariant transformation) \\ = \frac{1}{\sqrt{3}} (for power invariant transformation) \end{array}$

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties


ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).
SharingFactor	Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing (HDL Coder).

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced in R2024b

6-Phase VSD Transform

Description

Examples

Field-Oriented Control of Six-Phase PMSM

Ports

Input

a₁b₁c₁ — First set of three-phase inputs
scalar

a₂b₂c₂ — Second set of three-phase inputs
scalar

Output

αβxyz₊z_- — Six axis components in three different subspaces
scalar

Parameters

Power invariant — Option to enable power invariant transformation
`off` (default) | on

Motor type — Type of six-phase PMSM
`Asymmetric (30 degree offset)` (default) | `Symmetric (60 degree offset)`

Algorithms

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Topics

6-Phase VSD Transform

Description

Examples

Field-Oriented Control of Six-Phase PMSM

Ports

Input

a1b1c1 — First set of three-phase inputs scalar

a2b2c2 — Second set of three-phase inputs scalar

Output

αβxyz+z- — Six axis components in three different subspaces scalar

Parameters

Power invariant — Option to enable power invariant transformation off (default) | on

Motor type — Type of six-phase PMSM Asymmetric (30 degree offset) (default) | Symmetric (60 degree offset)

Algorithms

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Topics

a₁b₁c₁ — First set of three-phase inputs
scalar

a₂b₂c₂ — Second set of three-phase inputs
scalar

αβxyz₊z_- — Six axis components in three different subspaces
scalar

Power invariant — Option to enable power invariant transformation
`off` (default) | on

Motor type — Type of six-phase PMSM
`Asymmetric (30 degree offset)` (default) | `Symmetric (60 degree offset)`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.