sldvextract
Extract subsystem or subchart contents into new model for analysis
Syntax
Description
extracts the contents of the atomic subsystem newModel
= sldvextract(subsystem
)subsystem
and
creates a model for the Simulink®
Design Verifier™ software to analyze. sldvextract
returns the name
of the new model in newModel
. If the model name exists,
sldvextract
uses the subsystem name for the model name,
appending a number to the model name.
extracts the contents of the atomic subchart newModel
= sldvextract(subchart
)subchart
and
creates a model for the Simulink
Design Verifier software to analyze. Specify the full path of the atomic subchart in
subchart
. If the model name exists,
sldvextract
uses the subchart name for the model name,
appending a number to the model name.
Note
If the atomic subchart calls an exported graphical function that is
outside the subchart, sldvextract
creates the model, but
the new model will not compile.
creates a scheduler model that invokes the export-function model
newModel
= sldvextract(exportfcnmodel
)exportfcnmodel
for analysis by Simulink
Design Verifier. sldvextract
returns the name of the new model in
newModel
. The newModel
consists of
exportfcnmodel
model name with a suffix
SldvScheduler
. If the model name already exists,
sldvextract
uses the exportfcnmodel
name for the model name, appending a number to the model name.
extracts a stub model for the model newModel
= sldvextract(modelmissingslfunctiondef
)modelmissingslfunctiondef
which has missing Simulink function definitions for the Simulink
Design Verifier to analyze. It returns the name of the new model in
newModel
. sldvextract
uses the input
model name with a suffix SldvStub
for the extracted model name,
appending a numeral to the model name if that model name already exists.
opens the extracted model if you set newModel
= sldvextract(modelmissingslfunctiondef
, showModel
)showModel
to
true
. Extracted model will be only loaded if
showModel
is set to false
.
Examples
Input Arguments
Output Arguments
Limitations
Simulink Design Verifier does not support extraction when:
A subsystem has reinitialize ports. For more information, see Reinitialize States of Blocks in Subsystem.
A model block has Initialize, Reset, Reinitialize, or Terminate event ports. For more information, see Model Events Simulation.
Version History
Introduced in R2007a