Area Optimization

RAM mapping, resource sharing, and streaming

Reduce the resource usage of your design on a target FPGA or SoC device by applying area optimizations. You can reduce the area needed by your design by using RAM mapping, resource sharing, streaming, and other area optimizations. For an overview on area optimizations, see Speed and Area Optimizations in HDL Coder.

Topics

Apply RAM Mapping to Optimize Area
Map elements to RAM to optimize area on your target hardware.
RAM Mapping with the MATLAB Function Block
How to use RAM mapping optimization with MapPersistentVarsToRAM parameter for MATLAB Function blocks in your model.
Map Matrices to ROM
To map a matrix constant to ROM:If your MATLAB^® code meets these requirements, HDL Coder™ inserts a no-reset register at the output of the matrix in the generated code.
Resource Sharing
How to use resource sharing to save chip area.
Streaming
What is streaming and how to use the optimization to save resources.
Find Feedback Loops
Highlight feedback loops that are inhibiting optimizations.
Subsystem Optimizations for Filters
Select resource sharing and pipeline optimization options.
HDL Optimizations Across MATLAB Function Block Boundary Using MATLAB Datapath Architecture
Apply optimizations inside and across MATLAB Function blocks with other Simulink^® blocks.
Configure Custom Synthesis Attributes for Simulink Blocks
This example shows how to configure custom synthesis attributes for the model and propagate them to the generated HDL code.

Featured Examples

Getting Started with RAM and ROM in Simulink

Utilize RAM resources in your FPGA design using HDL Coder™.

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Streaming: Area Optimization

Use the subsystem level streaming optimization in HDL Coder™.

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Resource Sharing for Area Optimization

Use the subsystem level sharing optimization in HDL Coder™.

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Single-Rate Resource Sharing Architecture

How HDL Coder™ generates a single-rate architecture from a model to manage the execution of operations in the context of clock-rate pipelining and resource sharing. When you apply resource sharing to blocks in your design, HDL Coder decides the architecture to use based on the sample rate of the regions where sharing occurs. If resource sharing occurs in a region of the design that operates at the fastest base sample rate, then HDL Coder synthesizes a local multi-rate architecture, as described in Resource Sharing for Area Optimization. In this example, the shared resources are in a region that operates at a slower sample rate, so HDL Coder applies clock-rate pipelining and synthesizes a single-rate architecture.

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Improve Resource Sharing with Design Modifications

Improve opportunities for resource sharing to optimize your model design by making certain modifications to your design. Resource sharing is an HDL Coder optimization that improves area utilization in the design on the target FPGA device. The optimization identifies multiple functionally equivalent resources and replaces them with a single resource. For more information, see Resource Sharing.

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Improve Resource Sharing with Clone Detection and Replacement

Automatically identify and replace recurring patterns by using the Clone Detector App. Consequently, it also improves opportunities for optimizing the model by using resource sharing. The Clone Detector App refactors models by identifying clones in a design and replacing clones with links to subsystem blocks in a library. This example uses a model that has already been modified for optimal resource sharing by using the Clone Detector App. To learn more about these modifications, see "Improve Resource Sharing with Design Modifications."

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