RAM 和 ROM 模块
R2026b使用 HDL RAM 库中的模块在硬件上模拟 RAM 和 ROM
HDL Coder 模块库包含许多模块，您可将其添加到 Simulink® 建模环境并开发 HDL 算法。您可使用 HDL Coder 库中的模块在目标器件上模拟 RAM 和 ROM 模块。
要过滤 Simulink 库浏览器以仅显示 HDL 支持的模块，请输入 hdllib。
函数
hdllib | 显示与 HDL 代码生成兼容的模块 |
模块
 | Dual Port RAM System | Dual-port RAM that supports simultaneous read and write operations |
 | Dual Rate Dual Port RAM | Dual-port RAM that supports two rates |
 | HDL FIFO | Store sequence of input samples in first in, first out register |
 | Simple Dual Port RAM System | Simple dual-port RAM that supports simultaneous read and write operations |
 | Single Port RAM System | Single-port RAM that supports sequential read and write operations |
 | True Dual Port RAM System | True dual-port RAM that supports simultaneous read and write operations (自 R2023b 起) |
 | Simple Tri Port RAM System | Simple tri-port RAM that supports simultaneous read and write operations (自 R2023b 起) |
主题
- Map Matrices to ROM
Map matrices to implement ROM in MATLAB and Simulink.
- 使用 Simulink 模板进行 HDL 代码生成
使用 Simulink 模型模板进行 HDL 代码生成以创建高效的硬件设计。
- Map HDL FIFO Blocks to UltraRAM Resources on FPGA
Generate HDL code with synthesis attributes that enable UltraRAM inference for an HDL FIFO block on an FPGA. (自 R2026a 起)
精选示例
Get Started with RAM and ROM in Simulink
Configure RAM blocks in Simulink® to generate synthesizable HDL code by using HDL Coder™. The generated code can be mapped by synthesis tools to dedicated RAM resources available in FPGA devices. This example also shows how to model ROM behavior in Simulink.
