Domain experts and hardware engineers use MATLAB and Simulink to develop prototype and production applications for deployment on Intel® FPGA and SoC devices.
With MATLAB and Simulink, you can:
- Model hardware architecture at the system level
- Program your FPGA or SoC without writing any code
- Simulate and debug your FPGA or SoC using MATLAB and Simulink products
- Generate production HDL and C code for FPGA or SoC integration
“We have a wealth of experience in our domain but little experience with FPGA integration. Simulink and HDL Coder enabled us to focus on designing intelligent algorithms for our product and not on how to run those algorithms on a specific FPGA.”
Using MATLAB with Intel FPGAs and SoCs
Modeling and Simulation
Simulink for Model-Based Design enables you to reduce development time for Intel FPGA and SoC applications by modeling the hardware implementation at a high-level and simulating in the system context. Also, you can quantize to Fixed-Point Made Easy for FPGA Programming (30:45) for more efficient resource usage, or generate synthesizable Generate Floating-Point HDL for FPGA and ASIC Hardware (9:19) HDL to more easily program FPGAs.
HDL Coder generates synthesizable VHDL® or Verilog® directly from HDL-ready Simulink and MATLAB function blocks for applications such as signal processing, wireless communications, motor and power control, and image/video processing.
DSP Builder for Intel FPGAs adds Intel-specific blocks to Simulink for system-level simulation and hardware deployment. You can integrate DSP Builder blocks with native Simulink blocks for HDL code generation.
SoC Blockset lets you analyze the performance of hardware-software interaction for Intel SoC devices, including the use of memory and scheduling/OS effects.
Mix floating- and fixed-point operations in the same design. This trigonometric operation is implemented in floating-point using standard Intel FPGA resources.
Explore Products
Prototype of deploying a deep learning network to an Intel SoC platform from MATLAB and running inference from the MATLAB application.
Prototyping on FPGA- and SoC-Based Platforms
To get started prototyping, you can download support packages to target pre-configured Intel FPGA- and SoC-based evaluation platforms. HDL Coder then guides you through the steps to program your FPGA or SoC directly from Simulink without having to write HDL code. Rather than writing a Verilog testbench or a VHDL testbench, you can also verify your HDL code with MATLAB and Simulink testbenches using HDL cosimulation. Supported simulators include ModelSim™ and Questa™ from Siemens EDA and Cadence® Xcelium®.
You can choose from multiple techniques to debug your FPGA prototype directly from MATLAB and Simulink. Insert IP to: read or write to AXI registers and transfer large signal or image files between MATLAB and on-board memory locations; capture data from signals internal to the FPGA for analysis in MATLAB; or test your algorithm on an evaluation kit running FPGA-in-the-loop (2:52) with your MATLAB or Simulink testbench.
HDL and IP Core Generation for Production Integration
Most blocks that support HDL code generation feature HDL block properties that enable you to specify custom hardware implementation options such as pipeline insertion, resource sharing, and RAM mapping. HDL code generation settings let you globally customize optimizations, reset styles, clock enables, naming conventions, and more. Together with the ability to design implementation architectures in Simulink you have full control over speed and area optimization for Intel FPGA and SoC devices.
You can generate readable synthesizable RTL for integration with the non-algorithmic content in Quartus®. If you have installed the HDL Coder support package for Intel SoC, you can generate an IP core wrapper that is compatible with various AXI protocols for communication with the Arm® processor and other device components. You can use the Embedded Coder support package for Intel SoC to generate driver and application software to program the Arm application processor.
Reports from generated HDL and IP core. The IP Core Generation Report shows the mapping of design inputs and outputs to AXI registers and protocols.
Define a custom reference design with a placeholder with I/O mappings into which you can generate HDL.
Extending Target Platform Support
If you need to deploy to an FPGA- or SoC-based platform not included in a support package supplied by MathWorks, you can create or download a reference design and plug it into HDL Coder. You can develop the reference design using SoC Blockset or Quartus Prime.
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