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引导式代码生成

使用“配置参数”对话框和 Simulink HDL 工作流顾问进行引导式代码生成

您可以通过 UI 使用 Simulink® 工具条中的 HDL 代码选项卡或“配置参数”对话框生成 Simulink 模型的 HDL 代码。在此对话框中，您可以指定各种 HDL 代码生成设置，包括基本文件夹、语言选择以及更高级优化参数。要了解如何从 HDL 代码选项卡生成 HDL 代码，请参阅Generate HDL Code from Simulink Model。

要将生成的代码部署到目标设备，请使用 Simulink HDL 工作流顾问。该顾问可运行端到端工作流，以检查 HDL 兼容性并将生成的代码部署到目标设备。HDL 工作流顾问在 Simulink Online™ 中不可用。

函数

hdladvisorDisplay HDL Workflow Advisor
hdlsetup设置用于 HDL 代码生成的模型配置参数
hdlsetuptoolpath设置系统环境以访问 FPGA 综合软件

检查

Check for global reset setting for Xilinx and Altera devices
检查代数环

模型设置

全部展开

要生成 HDL 的模块Select subsystem or model for HDL code generation
语言HDL code generation language
代码生成文件夹Folder for generated HDL code
还原模型默认值Reset model-level HDL settings to default values
运行兼容性检查器Check subsystem compatibility for HDL code generation
生成Generate HDL code for subsystem or model
工作流Target workflow
工程文件夹Folder for workflow-specific files (自 R2023b 起)
目标平台Platform on which to deploy generated HDL code (自 R2023b 起)
综合工具Synthesis tool to target generated HDL code
系列Device chip family
设备Device name
包Device package name
速度Device speed value
参考设计Reference design to integrate with generated IP core (自 R2023b 起)
参考设计工具版本Option to warn for reference design version mismatch (自 R2023b 起)
忽略工具版本不匹配Warning in instances of reference design tool version mismatch (自 R2023b 起)
参考设计参数Table of parameters available for default reference designs (自 R2023b 起)
目标频率Clock frequency for generated HDL design

常规

将流水线延迟映射到 RAMMap pipeline registers in generated HDL code to RAM
RAM 映射阈值Specify minimum RAM size for mapping to block RAMs
变换非零初始值延迟Implement Delay blocks to have zero initial value in generated HDL code
删除未使用的端口Remove unused ports from design
基于使能的约束Enable multiple clock cycles for data to propagate between registers

流水线

允许设计延迟分布Allow distributed pipelining and delay absorption optimizations to move design delays
流水线分布优先级Priority for distributed pipelining and delay absorption optimizations
时钟频率流水线Insert pipeline registers at faster clock rate than data rate
允许 DUT 输出端口的时钟频率流水线Pass the outputs from DUT at clock rate
平衡时钟频率流水线 DUT 输出端口Synchronize DUT outputs while satisfying highest-latency requirements of outputs (自 R2022b 起)
分布式流水线Enable pipeline register distribution
使用综合估计执行分布式流水线Use synthesis timing estimates to guide pipeline register insertion (自 R2022a 起)
自适应流水线Insert adaptive pipeline registers
将查找表映射到 RAM Map lookup tables to block RAM (自 R2021b 起)

资源复用

复用加法器Share adders with resource sharing optimization
加法器复用最小位宽Minimum bit width required to share adders with resource sharing optimization
复用乘法器Share multipliers with resource sharing optimization
乘法器复用最小位宽Minimum bit width required to share multipliers with resource sharing optimization
乘法器提升阈值Maximum bitwidth difference for promoting and sharing smaller multipliers
乘法器分割阈值Maximum input bit width for partitions
Multiply-Add 模块Share Multiply-Add blocks with resource sharing optimization
Multiply-Add 模块复用最小位宽Minimum bit width required to share Multiply-Add blocks with resource sharing optimization
原子子系统Share Atomic Subsystem blocks with resource sharing optimization
MATLAB Function 模块Share MATLAB Function blocks with resource sharing optimization
浮点 IPShare floating-point IPs with resource sharing optimization

帧到采样的转换

启用帧到采样的转换Enable frame-to-sample conversion (自 R2022b 起)
每周期采样数Maximum size of streams for frame-to-sample conversion (自 R2022b 起)
输入 FIFO 大小Register size of generated input FIFOs around streaming matrix partitions (自 R2022b 起)
输出 FIFO 大小Register size of generated output FIFOs around streaming matrix partitions (自 R2022b 起)
输入处理顺序Processing order to use for frame inputs (自 R2023a 起)
启用外部存储的延迟大小阈值(位)Maximum delay size for external memory (自 R2023a 起)
使用浮点Use native floating-point library (自 R2023a 起)
延迟策略Specify latency strategy to use for floating-point values
处理非正规数Specify whether to handle denormal numbers
尾数乘法策略Specify how to implement mantissa multiplication operation
供应商特定浮点库Select vendor-specific floating-point library (自 R2023a 起)

全局设置

复位类型Reset logic to use for registers in HDL code
复位生效电平Active level of reset input signal
时钟输入端口Name for clock input port
时钟使能输入端口 Name for clock enable input port
复位输入端口Name for reset input port
时钟输入Generate single or multiple clock inputs
将 Simulink 速率视为实际硬件速率Set oversampling value based on model rates and target frequency values (自 R2023b 起)
时钟沿Active clock edge
过采样因子Oversampling value

常规

Verilog 文件扩展名File name extension for generated Verilog files
VHDL 文件扩展名File name extension for generated VHDL files
SystemVerilog 文件扩展名File name extension for generated SystemVerilog files (自 R2023b 起)
包后缀Text to append to model or subsystem name
实体冲突后缀Text to use to resolve duplicate module names
分割实体文件后缀Text to append to name of generated model file
保留字后缀Text to append to value names, postfix values, or labels
分割架构文件后缀Text to append to name of generated architecture file
钟控过程后缀Text to append to HDL clock process names
分割实体和架构Write architecture code to multiple VHDL files
复数实部后缀Text to append to real part of complex signal names
VHDL 架构名称Architecture name for DUT
复数虚部后缀Text to append to imaginary part of complex signal names
模块名称前缀Text to prefix to module or entity name in generated HDL code
使能前缀Base name for internal clock enables and other flow control signals
时序控制器后缀Text to append to timing controller name
流水线后缀Text to append to names of input or output pipeline registers
VHDL 库名称Target library name for generated VHDL code
将为模型引用生成的 VHDL 或 SystemVerilog 代码置于单一库中Generate VHDL or SystemVerilog code in separate libraries
模块生成标签Text to append to HDL GENERATE statements
输出生成标签Text to append to assignment blocks in VHDL GENERATE statements
实例生成标签Text to append to instance section labels
向量前缀Text to prefix to vector names
实例前缀Text to prefix to component instance names
实例后缀Text to append to component instance names
映射文件后缀Text to append to generated mapping file

端口

输入数据类型HDL data type for input ports of model
输出数据类型HDL data type for output ports of model
时钟使能输出端口Name for generated clock enable output port
尽量减少时钟使能Omit clock enable logic in generated code
尽量减少全局复位Omit reset logic in generated code
使用触发信号作为时钟Use trigger input signal as clock in generated code
生成可调参数的 HDL DUT 输入端口Create DUT input ports for tunable parameters (自 R2021b 起)
平衡生成的 DUT 输入端口的延迟Insert matching delays on generated DUT inport port paths (自 R2022b 起)
生成测试点的 HDL DUT 输出端口Create DUT output ports for test point signals
平衡生成的 DUT 输出端口的延迟Insert matching delays on generated DUT output port paths (自 R2022b 起)
端口标量化Flatten vector ports into structure of scalar ports
FPGA 部署的最大 I/O 引脚数Maximum number of I/O pins for target FPGA (自 R2022a 起)
检查 DUT 引脚数是否超出 I/O 阈值Option to generate error or warning when DUT pin count exceeds maximum number of I/O pins (自 R2023a 起)

编码风格

通过聚合体表示常量值Represent constants by using aggregates
内联 MATLAB Function 模块代码Inline HDL code for MATLAB Function blocks
初始化所有 RAM 模块Generate initial signal value for RAM blocks
RAM 架构Specify RAM architecture with or without clock enable
无复位寄存器初始化Specify how to initialize registers that do no reset
尽量减少中间信号Minimize intermediate signals in generated code
展开 For-Generate 循环Unroll and omit FOR and GENERATE loops from generated HDL code
从封装子系统生成参数化 HDL 代码Generate reusable HDL code for subsystems
枚举类型编码方案Specify encoding scheme to use for enumeration types
对寄存器使用 "rising_edge/falling_edge" 样式Use rising_edge or falling_edge to detect clock transitions in generated code
代码重用Specify whether to generate a reusable file for subsystems (自 R2022a 起)
内联 VHDL 配置Whether generated VHDL code includes inline configurations
串联类型安全零Whether to use type-safe syntax for concatenated zeros in generated VHDL code
生成经过混淆处理的 HDL 代码Whether to generate obfuscated HDL code
在生成的 HDL 代码中保留总线结构体Generate code with VHDL record or SystemVerilog structure types (自 R2022b 起)
标量化端口命名的索引Specify starting index for names of scalarized vector ports (自 R2022a 起)
优化时序控制器Generate one counter for each rate in timing controller code
时序控制器架构Specify architecture of generated timing controller
使用 Verilog 或 SystemVerilog 的 `timescale 指令Use compiler directives in generated Verilog or SystemVerilog code
Verilog 或 SystemVerilog 的 timescale 设定Specify timescale to use in generated Verilog or SystemVerilog code

编码标准

HDL 编码标准Select coding standard guidelines
在编码标准报告中显示通过规则Include passing rules in coding standard report
检查重复名称Check for duplicate names in design
检查设计名称中是否有 HDL 关键字Check for HDL keywords in design names
检查模块、实例和实体名称长度Whether to check module, instance, and entity name length
检查信号、端口和参数名称长度Whether to check signal, port, and parameter name length
检查时钟使能信号Whether to check for clock enable signals in generated code
检测复位信号的使用Whether to check for reset signals in generated code
检测异步复位信号的使用Whether to check for asynchronous reset signals in generated code
尽量减少变量的使用Whether to minimize use of variables
检查设置 RAM 初始值的初始语句Whether to check for initial statements that set RAM initial values
检查 process 中的条件语句Whether to check for length of conditional statements
检查多个级联控制区域中相同变量的赋值Whether to check if there are assignments to same variable in multiple cascaded control regions (自 R2021b 起)
检查 if-else 语句链长度Whether to check if-else statement chain length
检查 if-else 语句嵌套深度Whether to check if-else statement nesting depth
检查乘法器宽度Whether to check multiplier bit width
检查非整数常量Whether to check for non-integer constants
检查换行长度Whether to check line lengths in the generated HDL code

注释

启用注释启用或禁用注释
头部注释Comment lines in header of generated HDL and test bench files
在头部包括时间/日期戳Include time and date information in generated HDL file header
在模块注释中包含需求Include requirements as comments in code or code generation reports
自定义文件头部注释Custom comment in header of generated HDL code
自定义文件尾部注释Custom comment in footer of generated HDL code

模型生成

生成的模型Generate model that shows latency and numeric differences between model and HDL code
验证模型Generate validation model
验证模型的后缀Suffix to append to validation model name
生成的模型的前缀Prefix to append to generated model name
布局样式Layout style of generated HDL model (自 R2021b 起)
自动信号布线生成模型中信号的自动布线
模块间水平缩放Horizontal scaling of generated model
模块间垂直缩放Vertical scaling of generated model

高级

检查黑盒接口中是否存在名称冲突Generate warning or error when black box interfaces have name conflicts
检查生成的 HDL 代码中是否存在实数Generate warning or error when generated HDL code contains reals
生成 HDL 代码Enable code generation for model or subsystem
通过生成仅仿真索引检查来抑制越界访问错误Generate logic that prevents array indices from going out of bounds (自 R2022a 起)
生成可追溯性报告Generate report with hyperlinks from code to model and model to code
可追溯性样式Type of traceability to generate in code generation report
生成模型 Web 视图Include Web view in code generation report
生成资源利用率报告Generate resource utilization section in code generation report
生成优化报告Generate optimization sections in code generation report
生成高级时序关键路径报告Insert highlighting script that maps estimated critical path in code generation report
自定义时序数据库目录Path to custom timing files (自 R2021b 起)
仿真工具Simulator to use to run generated test benches
HDL 代码覆盖率Enable HDL code coverage flags in generated simulator scripts
HDL 测试平台Enable HDL test bench generation
联合仿真模型Generate cosimulation model
SystemVerilog DPI 测试平台Enable SystemVerilog DPI test bench generation
测试平台名称后缀Suffix to append to test bench name
强制时钟Whether test bench forces clock input signals
时钟高电平时间(ns)Period during which test bench drives clock input signals high
时钟低电平时间(ns)Period during which test bench drives clock input signals low
保持时间(ns)Hold time for input signals and forced reset input signals
强制时钟使能Whether test bench forces clock enable input signals
时钟使能延迟(以时钟周期为单位)Elapsed time between deassertion of reset and assertion of clock enable
强制复位Whether test bench forces reset input signals
复位长度(以时钟周期为单位)Length of time during which reset is asserted
保持采样之间的输入数据Hold data values for subrate signals for number of base-rate clock cycles in subrate sample period
初始化测试平台输入Specify initial value driven on test bench inputs before data is asserted to DUT
多文件测试平台Divide generated test bench into helper functions, data, and HDL test bench code files
测试平台数据文件名后缀Suffix to append to test bench data file name when generating multi-file test bench
测试平台参考后缀Suffix to append to names of reference signals generated in test bench code
使用文件 I/O 读取/写入测试平台数据Create data files for reading and writing test bench input and output data
忽略输出数据检查(采样数)Number of samples during which output data checking is suppressed
浮点容差检查依据Check for errors in floating-point library based on relative or ULP errors
容差值Floating-point tolerance value
仿真库路径Path of compiled Altera or Xilinx simulation libraries
生成 EDA 脚本Enable generation of third-party electronic design automation script files
编译文件后缀Postfix to append to DUT or test bench name for compilation script file name
编译初始化Format name to use to write Init section of compilation script
编译 VHDL 的命令Format name to use to write Cmd section of compilation script for VHDL
编译 Verilog 或 SystemVerilog 的命令Format name to use to write Cmd section of compilation script for Verilog or SystemVerilog
编译终止Format name to use to write termination section of compilation script
仿真文件后缀Postfix to append to DUT or test bench name
仿真初始化Format name to use to write initialization section of simulation script
仿真命令用于写入仿真命令的格式名称
仿真波形查看命令Waveform viewing command to write to simulation script
仿真终止Format name to write to write termination section of simulation script
仿真器标志Simulator flags to apply to generated compilation scripts
选择综合工具Specify synthesis tool for which to generate synthesis scripts
综合文件后缀Postfix to append to file name
综合初始化Format name to use to write initialization section of synthesis script
综合命令Format name to use to write synthesis command
综合终止Format name to use to write termination section of synthesis script
要添加到综合工程的附加文件Additional HDL or constraint files
选择 HDL lint 工具Specify HDL lint tool for which to generate lint scripts
Lint 初始化Format name to use to write initialization section of HDL lint script
Lint 命令Format name to use to write command for HDL lint script
Lint 终止Format to use to write termination section of HDL lint script

主题

使用 HDL 工作流顾问

使用“模型配置参数”对话框

模型配置参数