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Model Compatibility Checks

Description of the HDL Code Advisor, and how to use it to check and update your model for compatibility with HDL code generation

Use the HDL Code Advisor or the HDL Coder checks in the Model Advisor to verify and update your Simulink® model or subsystem for compatibility with HDL code generation. You can select and run the checks for model configuration, native floating-point support, and industry-standard guidelines. When you run the checks, the Code Advisor displays the result as a pass or a fail. For a fail status, the Code Advisor lists model settings or conditions that are not compliant with HDL Coder™. You can fix warnings or failures by using the Code Advisor recommended settings

Functions

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hdlcodeadvisorOpen HDL Code Advisor
modeladvisorOpen Model Advisor
checkhdlCheck subsystem or model for HDL code generation compatibility
hdllibDisplay blocks that are compatible with HDL code generation
hdlsetupSet up model parameters for HDL code generation

Checks

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Model configuration checks overview
Check for model parameters suited for HDL code generation
Check for global reset setting for Xilinx and Altera devices
Check inline configurations setting
Check algebraic loops
Check for visualization settings
Check delay balancing setting
Check for ports and subsystems overview
Check for invalid top level subsystem
Check for blocks and block settings overview
Check for infinite and continuous sample time sources
Check for unsupported blocks
Identify unconnected lines, input ports, and output ports
Check for MATLAB Function block settings
Check for Stateflow chart settings
Check for obsolete Unit Delay Enabled/Resettable Blocks
Check for blocks that have nonzero output latency
Check for unsupported storage class for signal objects
Check for Trigonometric Function block for LUT-based approximation method
Check for HDL Reciprocal block usage
Native Floating Point Checks Overview
Check for single datatypes in the model
Check for double data types in the model
Check for Data Type Conversion blocks with incompatible settings
Check for Relational Operator block usage
Check for HDL Reciprocal block usage
Check for unsupported blocks with Native Floating Point
Check blocks with nonzero ULP error

Guidelines Overview

Industry standard checks overview

Guidelines Specific to VHDL

Check file extension
Check generics
Check architecture name
Check entity and architecture

Guidelines for Clocks and Resets

Check clock, reset, and enable signals
Check clock settings

Naming Guidelines

Check naming conventions
Check top-level subsystem/port names
Check module/entity names
Check signal and port names
Check package file names

Topics

Related Information