Deploy IP Core on Custom Hardware

R2026b

Integrate generated IP cores into SoC device, Speedgoat I/O module, or standalone FPGA board by defining custom board and reference design

HDL Coder™ supports a limited set of preexisting target platforms. While these platforms are suitable for rapid prototyping, production workflows typically require a custom platform. Create a custom platform to integrate the IP core into a standalone FPGA board or SoC platform by using AMD^® Vivado^® IP Integrator.

You can define a custom reference design in MATLAB^® and use HDL Coder to integrate the IP core into that design.

For more details about the workflow, see Targeting FPGA and SoC Hardware Overview (HDL Coder).

Create a custom hardware platform workflow

Classes

`hdlcoder.Board`	Board registration object that describes SoC custom board
`hdlcoder.WorkflowConfig`	Configure HDL code generation and deployment workflows
`hdlcoder.ReferenceDesign`	Reference design registration object that describes SoC reference design
`hdlcoder.sdr`	Create transmitter and receiver for AD936x-based software-defined radio hardware (Since R2024a)

Functions

expand all

Board and Reference Design

`addCustomEDKDesign`	Specify Xilinx EDK MHS project file
`addCustomVivadoDesign`	Specify Xilinx Vivado exported block design Tcl file
`addIPRepository`	Include IP modules from your IP repository folder in your custom reference design
`addParameter`	Add and define custom parameters for your reference design
`validateReferenceDesign`	Check property values in reference design object
`validateBoard`	Check property values in board object

Add Interfaces

`addEthernetMACInterface`	Define Ethernet MAC interface for board object (Since R2022b)
`addExternalIOInterface`	Define external IO interface for board object
`addExternalPortInterface`	Define external port interface for board object
`addFPGADataCaptureInterface`	Add and define FPGA Data Capture interface (Since R2025a)
`addInternalIOInterface`	Add and define internal IO interface between generated IP core and existing IP cores
`addAXI4MasterInterface`	Add and define AXI4 Master interface
`addRegisterInterface`	Add and define register interface using AXI4 and AXI4-Lite protocol
`addAXI4StreamInterface`	Add AXI4-Stream interface
`addAXI4StreamVideoInterface`	Add AXI4-Stream Video interface
`addClockInterface`	Add clock and reset interface
`addMemoryInterface`	Access memory regions on your FPGA or SoC hardware (Since R2023a)

Callback Functions

`CallbackCustomProgrammingMethod`	Function handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
`CustomizeReferenceDesignFcn`	Function handle for callback function that gets executed before Set Target Interface task in the HDL Workflow Advisor
`PostBuildBitstreamFcn`	Function handle for callback function that gets executed after the build FPGA bitstream task runs
`PostCreateProjectFcn`	Function handle for callback function that gets executed after the create project task runs
`PostSWInterfaceFcn`	Function handle for custom callback function that gets executed after the generate software interface task runs
`PostTargetInterfaceFcn`	Function handle for callback function that gets executed after the set target interface task runs
`PostTargetReferenceDesignFcn`	Function handle for callback function that gets executed after the target reference design is set

Device Tree Generation

`addDeviceTree`	Add device tree for board object
`addIncludeFolder`	Specify the path of an include file to compile the device tree against
`addDeviceTree`	Add device tree for reference design object
`addIncludeFolder`	Specify a folder path for device tree include files and interface-specific fragment files

Export Reference Design

socExportReferenceDesign Export custom reference design for HDL Workflow Advisor

Topics

Board and Reference Design

Board and Reference Design Registration System (HDL Coder)
System for defining and registering boards and reference designs.
Register a Custom Board (HDL Coder)
Define the interface and attributes of a custom SoC board. After defining the board, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Register a Custom Reference Design (HDL Coder)
Define the interface and attributes of a custom SoC reference design. After defining and registering the reference design, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Define Custom Parameters and Callback Functions for Custom Reference Design (HDL Coder)
Learn how to define custom parameters and custom callback functions for your custom reference design.
Customize Reference Design Dynamically Based on Reference Design Parameters (HDL Coder)
Learn how to customize the reference design dynamically by using the CustomizeReferenceDesignFcn method.
Define and Add IP Repository to Custom Reference Design (HDL Coder)
Learn how you can create an IP repository and add the IP modules in the repository to your custom reference design.
Define Multiple AXI Master Interfaces in Reference Designs to Access DUT AXI4 Subordinate Interface (HDL Coder)
Learn how you can specify multiple AXI Master interfaces in the custom reference design to access HDL DUT IP AXI4 subordinate interface.
Generate HDL IP Core with Multiple AXI4-Stream and AXI4 Master Interfaces (HDL Coder)
Learn how you can map your DUT ports to multiple AXI4-Stream, AXI4-Stream Video, and AXI4 Master interfaces.
Use Callback Functions in Custom Reference Design (HDL Coder)
This example illustrates how to customize the reference design dynamically by using a callback function based on the reference design parameter options.
IP Caching for Faster Reference Design Synthesis (HDL Coder)
Use IP caching to speed up reference design synthesis time by using an out-of-context workflow.
Generate Device Tree for IP Core (HDL Coder)
Generate device tree files that include the HDL Coder generated IP core.
Export Custom Reference Design from SoC Model
Use the socExportReferenceDesign function to export a custom reference design from an SoC Blockset™ for AMD model.
Deploy IP Core With Auto-Generated Reference Design
Generate and deploy an IP core to an AMD SoC board without selecting or authoring a pre-existing reference design. (Since R2026b)

Specific Hardware Platforms

Define Custom Board and Reference Design for AMD Workflow (HDL Coder)
This example shows how to define and register a custom board and custom reference design in the Zynq® workflow.
Build Custom Linux Image for IP Core (HDL Coder)
This example shows how to set up a build environment and create a Linux® image for an IP core for the Digilent Zybo™ Z7-10 Zynq® board by using the MathWorks® build system.
Define Custom Board and Reference Design for Zynq Ultrascale+ MPSoC Workflow (HDL Coder)
This example shows how to define and register a custom board and reference design for the Zynq® workflow using a Xilinx® Zynq UltraScale+™ MPSoC ZCU104 evaluation kit.
Build Custom Reference Design to Interface with Peripheral Chip (HDL Coder)
This example shows how to build a reference design to run an audio algorithm and access audio input and output on a Zynq® board.
Authoring a Reference Design for Audio System on a ZYBO Board (HDL Coder)
This example shows how to build a reference design to run an audio algorithm and access audio input and output on ZYBO™ Z7-10 board.
Define Custom Board and Reference Design for AMD Kria KR260 Robotics Kit
Set up a custom KR260 board and reference design to enable IP core generation and control LEDs. (Since R2026a)
Define Custom Board and Reference Design for AMD Kria KV260 Vision AI Starter Kit
Set up a custom KV260 board and reference design to enable IP core generation and control LEDs. (Since R2026a)

Related Information

Troubleshooting

Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows (HDL Coder)

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.

SD Card Cannot Boot Board

Troubleshoot hardware connection issues.

Featured Examples

Implement an Audio Filter on a Zynq Board

Model an audio system and implement it on a Zynq® board using an audio reference design.

(HDL Coder)