Tim McBrayer

MathWorks

自 2011 起处于活动状态

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Software developer for MathWorks working on HDL Coder.

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Import verilog o vhdl in simulink
You can integrate your HDL code with a Simulink design during HDL code generation. There is no way to import the logic in to Sim...

6 years 前 | 0

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Do not generate a seperate module for the subsystem when Generating HDL code
Yes, this is a native capability of HDL Coder. Each subsystem has a HDL Block property named "FlattenHierarchy" that can be eith...

6 years 前 | 1

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Using Reference Model for HDL code Generation
Mark each instance of the subsystem as atomic. When marked atomic, it will generate only one output file for all instances. ...

6 years 前 | 1

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buffer block inside enabled subsystem
As the error message states, all ports of an enabled subsystem must be the same rate, for HDL code generation. From your image I...

6 years 前 | 0

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hdl code generation for function block
Are you attempting to process single data types with your MATLAB Function block? This isn't supported by HDL Coder. In addition,...

6 years 前 | 0

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i want to convert the following matlab code to verilog code using sysgen. i am new to sysgen.For that what is the procedure to do?
By "sysgen", I am assuming that you are referring to <https://www.xilinx.com/products/design-tools/vivado/integration/sysgen.htm...

6 years 前 | 0

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Issue unexpected output from hdlcoder
This looks like an issue with your data types. Note that your output Verilog code has the output being a 4-bit value. You don't ...

6 years 前 | 2

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HDL Code Generation 2D-matrices
The only current way to do this is by implementing your own matrix multiplication. You will need 200000 * 4 * 4 = 3200000 multip...

6 years 前 | 0

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error in hdl code
The error is that you do not have a license for the lte_toolbox. You need to do one of the following: If you do have a licens...

6 years 前 | 0

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HDL code generation error.
You can place your enabled subsystem inside another subsystem. This should allow you to generate DHL code for the design.

6 years 前 | 0

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How to share multipliers while generating VHDL code in HDL Coder
The sharing factor is available on each Subsystem as a HDL Block property, and is applied to all sharable content contained unde...

6 years 前 | 0

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Generate HDL code from SVM function in Matlab.
The R2016a list of built-in MATLAB functions supported for HDL code generation can be found at <https://www.mathworks.com/help/r...

6 years 前 | 0

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generation matlab to VHDL
I'm not sure you want to be attempting to perform HLS on HDL source code. HLS is normally a C/C++ based flow, not an HDL flow. I...

6 years 前 | 0

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Using Unit Delays in triggered Subsystems for HDL Codegeneration
This should work fine, and does in a small test I just tried. Can you open a customer support case so that this may be further i...

6 years 前 | 0

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Generate HDL code from simulink
There is no ability in HDL Coder to import .scs or .ckt files.

6 years 前 | 0

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how can i convert inbuilt functions of matlab like svd in vhdl language.
The list of MATLAB functions supported for HDL Code generation are in the documentation. The R2017a list is at http://www.mathwo...

6 years 前 | 0

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Generating HDL code for look up table
The short answer is no, HDL Coder cannot do this. This is because you are asking for hardware to look up two values at the same ...

7 years 前 | 0

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CLK_Enable HDL coder
I understand your confusion; the wording of this message should more properly refer to 'clk', and not 'clk_enable'. Your desi...

7 years 前 | 0

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makehdl like functionality for MATLAB Algorithm HDL generation
Native Floating Point code generation support was introduced in HDL Coder in R2017a for Simulink models. To instantiate a |floor...

7 years 前 | 0

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HDL Coder Clock Summary Explanation
The clock report is primarily intended to show the relationship between the various signal rates. As you have noted, these times...

7 years 前 | 0

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Can I convert .vhdl handwrt into .m or directly to sim block?
The only currently available capability for combining HDL and Simulink is to use HDL Verifier to co-simulate your HDL in ModelSi...

7 years 前 | 0

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Best way to do a dynamic bit slice?
Simulink has limited bit-manipulation capabilities; it's designed to address a higher level of abstraction, for the most part. T...

7 years 前 | 0

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please help sir !!! how can i fix that the HDL check report errors
HDL Coder does not support matrices for code generation. You will need to convert your frame-based design into a pixel-based des...

7 years 前 | 0

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HDL Coder reset control
Andrew, There is a block-level parameter that allows the reset to be disabled on a block by block basis. You can access this...

7 years 前 | 3

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is there a way to work with enabled subsystems when generating hdl code?
What is the data type of the Simulink signal feeding into the Enable port? It must be a scalar and either a |boolean| or a |ufix...

7 years 前 | 0

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Conversion of GMM in MATLAB Code to VHDL using HDL Coder
You mention Simulink, but then discuss generating code from MATLAB if I understand correctly. I will answer as if you are genera...

7 years 前 | 1

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how can i implement sobel edge detector using Simulink on FPGA?
The simplest answer is that you need the HDL Coder product in order to generate HDL code from a Simulink model. The links that W...

7 years 前 | 0

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Hi, I'm trying to generate a VHDL code from Hdl coder. My function file is like below.
You will need to use some other method of informing your loop when to stop iterating. Hardware designs require fixed sizes for b...

7 years 前 | 0

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HDL Coder, Bus and Black Box
HDL Coder gained bus support for black box HDL architectures in R2015b. Is there a chance you can update your MATLAB release? ...

7 years 前 | 0

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i get the error when i m trying to generate the hdl code for a matlab program by hdl coder... the error is 'In emlhdlcoder.WorkFlow.Manager/wfa_generateCode (line 627)'... help me to solve this error.. thanks in advance..
It's hard to say what your immediate problem is with no error message listed, but I strongly suspect that you are using function...

7 years 前 | 0

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