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基本 HDL 算法
R2026aHDL Coder 模块库包含许多基本模块，您可将其添加到 Simulink 建模环境并开发 HDL 算法。这些模块包括输入源、输出信宿及执行基础到复杂数学和三角运算的模块。
要过滤 Simulink 库浏览器以仅显示 HDL 支持的模块，请输入 hdllib。本节列出的模块包括仅在 HDL Coder 库中可用的模块。Add 和 Product 等模块在库浏览器的 Simulink 库中提供。
有关过滤后的支持 HDL 代码生成的 Simulink 模块的列表，请参阅 Simulink 模块列表（HDL 代码生成）。
函数
hdllib | 显示与 HDL 代码生成兼容的模块 |
检查
模块
 | Bit Concat | Concatenates up to 128 input words into single output |
 | Bit Reduce | 对所有输入信号位进行 AND、OR 或 XOR 位归约，结果为单个位 |
 | Bit Rotate | 按位的位置旋转输入信号 |
 | Bit Shift | 输入信号的逻辑或算术移位 |
 | Bit Slice | 从输入信号返回连续位字段 |
 | Bits to Word | Convert vector of bits to integer (自 R2023a 起) |
 | Word to Bits | Converts real numbers to vector of bits (自 R2023a 起) |
 | Sine HDL Optimized and Cosine HDL Optimized | Implement fixed-point sine and cosine wave by using lookup table approach optimized for HDL code generation |
 | HDL Counter | Free-running, count-limited, or modulo hardware counter |
 | Atan2 | 使用 CORDIC 逼近方法计算 Atan2 运算，并进行带延迟的仿真 |
 | Sin | 使用 CORDIC 逼近方法计算正弦运算并带延迟进行仿真 |
 | Cos | 使用 CORDIC 逼近方法计算余弦运算并带延迟进行仿真 |
 | Cos+jSin | Compute Cos+jSin operation using CORDIC approximation method and
simulate with latency |
 | SinCos | Compute SinCos operation using CORDIC approximation method and
simulate with latency |
 | rSqrt | Compute reciprocal square-root operation and simulate with latency |
 | Sqrt | Compute Sqrt operation and simulate with latency |
 | SqrtLUT | Compute square-root operation using lookup table (自 R2026a 起) |
 | Divide | Compute division operation and simulate with latency |
 | Reciprocal | Compute reciprocal operation and simulate with latency |
主题
基础建模
- Use Test Points to Debug Signals with HDL Coder
An example that shows how to add test points to signals in your model and debug these signals in the generated HDL code. - Generate DUT Ports for Tunable Parameters
Generate tunable parameters as top-level DUT ports. - Add Comments to Generated HDL Code
Add comments to generated HDL code by using Simulink annotations, signal descriptions, DocBlock blocks, or requirement links. - Scalarization of Vector Ports in Generated VHDL Code
Flatten vector signals on entire model or at DUT level into a structure of scalar signals in generated VHDL or SystemVerilog code. - 对 Float Typecast 模块进行仿真并为其生成 HDL 代码
使用 Float Typecast 模块将输入强制转换为浮点或定点。
数据类型支持
- Supported Data Types and Scope
MATLAB® data type and scope support for HDL code generation. - Signal and Data Type Support
HDL code generation support for signal types and data types.
精选示例
使用 HDL Coder 实现基于控制信号的数学函数
HDL Coder™ 提供具有基于控制信号的定点数学函数的 HDLMathLib 模块。这些模块具有指示输入和输出数据是否有效的控制信号。您还可以对这些模块进行带延迟的仿真。
Implement Sqrt Block with Control Signals
Implement the control-signal based Square root block and use it to generate HDL code.
Implement rSqrt Block with Control Signals
Implement the control-signal based reciprocal square root block and use it to generate HDL code.
Implement Divide Block with Control Signals
Implement the control-signal based Divide block and use it to generate HDL code.
Implement Reciprocal Block with Control Signals
Implement the control-signal based Reciprocal block and use it to generate HDL code.
Implement Atan2 Block with Control Signals
Implement the control-signal based Atan2 block and use it to generate HDL code.
Implement Sine and Cosine Block with Control Signals
Implement the control-signal based SinCos block and use it to generate HDL code.
将位输入向量转换为整数
此示例说明如何在 Simulink® 模型中使用 Bits to Word 模块，该模型将位向量转换为无符号整数。您还为该模型生成 HDL 代码。
将整数转换为位向量
此示例说明如何在 Simulink® 模型中实现 Word to Bits 模块，该模型将整数转换为位向量。您还为该模型生成 HDL 代码。
