Unsupported Simulink Blocks in Analysis

R2026b

If Simulink^® Design Verifier™ is unable to analyze a model element, the tool attempts to stub the element and continue analyzing the model with the stub in place. For more information, see Handle Model Complexities with Automatic Stubbing. However, if stubbing is not possible, Simulink Design Verifier considers the model element as unsupported, and the model is incompatible for analysis.

The sections below describe model elements that are supported or not supported for analysis, including unsupported blocks and other limitations.

Commonly Used Blocks Library

The Commonly Used Blocks library includes blocks from other libraries. Unsupported blocks from the Commonly Used Blocks library are listed here under their respective libraries.

Continuous Library

Simulink Design Verifier does not support blocks from the Continuous library except for the Descriptor State-Space block.

Discontinuities Library

Simulink Design Verifier supports all blocks in the Discontinuities library.

Discrete Library

Simulink Design Verifier does not support Discrete State-Space and Discrete Zero-Pole blocks from the Discrete library.

Logic and Bit Operations Library

Simulink Design Verifier does not support Logical Operator block when it has more than 100 inputs.

Lookup Tables Library

Simulink Design Verifier does not support these blocks when Interpolation method or Extrapolation method is set to Akima Spline:

Math Operations Library

Simulink Design Verifier supports all block from Math Operations library.

Model Verification Library

Simulink Design Verifier supports all blocks in the Model Verification library.

Model-Wide Utilities Library

Simulink Design Verifier does not support Timed-Based Linearization and Trigger-Based Linearization blocks from the Model-Wide Utilities library.

Ports & Subsystems Library

Simulink Design Verifier does not support these blocks from the Ports and Subsystems library:

Block	Support Notes
Enabled Subsystem	Design range checks do not consider specified minimum and maximum values for blocks connected to the output port of the subsystem. For more information on design range checks, see Check for Specified Minimum and Maximum Value Violations. Simulink Design Verifier treats Enabled Subsystems as short-circuited during test generation.
Enabled and Triggered Subsystem	Not supported when the trigger control signal specifies a fixed-point data type. Design range checks do not consider specified minimum and maximum values for blocks connected to the output port of the subsystem. For more information on design range checks, see Check for Specified Minimum and Maximum Value Violations. Simulink Design Verifier treats Enabled and Triggered Subsystems as short-circuited during test generation.
Function-Call Subsystem	Design range checks do not consider specified minimum and maximum values for blocks connected to the output port of the subsystem. For more information on design range checks, see Check for Specified Minimum and Maximum Value Violations.
Function Element	Not supported.
Function Element Call	Not supported.
In Bus Element	Not supported for Software-in-the-Loop (SIL) code analysis.
Message Polling Subsystem	Not supported.
Message Triggered Subsystem	Not supported.
Triggered Subsystem	Not supported when the trigger control signal specifies a fixed-point data type. Design range checks do not consider specified minimum and maximum values for blocks connected to the output port of the subsystem. For more information on design range checks, see Check for Specified Minimum and Maximum Value Violations. Simulink Design Verifier treats Enabled Subsystems as short-circuited during test generation.
Variant Subsystem	Simulink Design Verifier analyzes all variant choices when Variant activation time is set to `startup`. For remaining types of Variant activation time, Simulink Design Verifier analyzes only the active variant choice.

Signal Attributes Library

Simulink Design Verifier supports all blocks in the Signal Attributes library.

Signal Routing Library

Simulink Design Verifier does not support these blocks from the Signal Routing library:

Block	Support Notes
Manual Switch	The Manual Switch block is compatible with the software, but the analysis ignores this block in a model. The analysis does not flag the coverage objectives for this block as satisfiable or unsatisfiable. Model coverage data is collected for the Manual Switch block.
Parameter Writer	Not supported.

Block

Support Notes

Manual Switch

The Manual Switch block is compatible with the software, but the analysis ignores this block in a model. The analysis does not flag the coverage objectives for this block as satisfiable or unsatisfiable.

Model coverage data is collected for the Manual Switch block.

Parameter Writer

Not supported.

Sinks Library

Simulink Design Verifier does not support Record and Stop Simulation blocks from the Sinks library.

Sources Library

Simulink Design Verifier does not support these blocks from the Sources library:

Block	Support Notes
Band-Limited White Noise	Not supported.
Constant	Not supported if Constant value is `inf` or `nan`.
From File	Not supported when MAT file data is stored in MATLAB^® `timeseries` format
From Spreadsheet	Not supported.
In Bus Element	Supported if `Simulink.Bus` type is defined for the In Bus Element block.
Playback	Not supported.
Random Number	Not supported.
Signal Editor	Not supported.
Signal Generator	Not supported if wave form is `random`.
Uniform Random Number	Not supported.

User-Defined Functions Library

Simulink Design Verifier does not support these blocks from the User-Defined Functions library:

Block	Support Notes
Initialize Function	Not Supported for Initialize function containing Parameter Writer blocks. Not supported as a target for subsystem analysis.
Level-2 MATLAB S-Function	Not supported.
MATLAB Function	Supported. For limitations, see Simulink Design Verifier Limitations for MATLAB for Code Generation
MATLAB System	Decision, Condition and MCDC Coverage objectives are supported in Test Generation. Enhanced MCDC, Relational Boundary and Custom Test objectives are not supported. Custom Proof objectives are not supported in Property Proving. Logical expressions within assignment statements are not analyzed for coverage objectives. For further limitations, see Simulink Design Verifier Limitations for MATLAB for Code Generation.
S-Function Builder	Supported. For limitations, see Simulink Design Verifier Limitations and Considerations for S-Functions and C/C++ Code.
Simulink Function	For export-function models, see Analyze Export-Function Models. Global Simulink functions within a non export-function model reference are not supported.
Observer Reference (Simulink Test)	Supported.

Additional Math and Discrete Library

Simulink Design Verifier supports all blocks in the Additional Math and Discrete library.

Toolbox Libraries

Simulink Design Verifier supports all blocks in the toolbox libraries except these:

Simscape™
Vehicle Network Toolbox™

Unsupported Simulink Blocks in Analysis

See Also

Topics